4355 is a positive voltage ideal diode-OR control-
ler that drives two external N-channel MOSFETs. Forming
the diode-OR with N-channel MOSFETs instead of Schottky
diodes reduces power consumption, heat dissipation and
PC board area.
With the LTC4355, power sources can easily be ORed
together to increase total system reliability. The LTC4355
can diode-OR two positive supplies or the return paths of
two negative supplies, such as in a –48V system.
In the forward direction the LTC4355 controls the volt-
age drop across the MOSFET to ensure smooth current
transfer from one path to the other without oscillation. If
a power source fails or is shorted, fast turnoff minimizes
reverse current transients.
Power fault detection indicates if the input supplies are
not in regulation, the inline fuses are blown, or the volt-
ages across the MOSFETs are greater than the fault
threshold.
Replaces Power Schottky Diodes
Controls N-Channel MOSFETs
0.3μs Turn-Off Time Limits Peak Fault Current
Wide Operating Voltage Range: 9V to 80V
Smooth Switchover without Oscillation
No Reverse DC Current
Monitors V
IN
, Fuse, and MOSFET Diode
Available in 14-Lead (4mm
×
3mm) DFN,
16-Lead MS and SO Packages
APPLICATIONS
n
n
n
n
High Availability Systems
AdvancedTCA
®
(ATCA) Systems
+48V and –48V Distributed Power Systems
Telecom Infrastructure
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
+48V Diode-OR
7A
V
IN1
= +48V
7A
V
IN2
= +48V
FDB3632
TO
LOAD
POWER DISSIPATION (W)
FDB3632
22k
340k
340k
IN1
MON1
SET
MON2
12.7k
GND
4355 TA01
Power Dissipation vs Load Current
6
5
DIODE (MBR10100)
4
3
2
1
FET (FDB3632)
0
0
2
4
6
CURRENT (A)
8
10
4355 TA02
22k
22k
22k
22k
GATE1 IN2
GATE2 OUT
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
POWER
SAVED
LTC4355
GND
12.7k
GREEN LEDs
PANASONIC LN1351C
4355fe
1
LTC4355
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages
IN1, IN2 .................................................. –1V to 100V
OUT ..................................................... –0.3V to 100V
Input Voltages
MON1, MON2, SET .................................. –0.3V to 7V
Output Voltages
GATE1 (Note 3) ................... V
IN1
– 0.2V to V
IN1
+ 13V
GATE2 (Note 3) ................... V
IN2
– 0.2V to V
IN2
+ 13V
PWRFLT1, PWRFLT2, VDSFLT,
FUSEFLT1, FUSEFLT2
............................... –0.3V to 8V
Operating Temperature Range
LTC4355C ................................................ 0°C to 70°C
LTC4355I..............................................–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS, SO Packages ............................................. 300°C
PIN CONFIGURATION
TOP VIEW
IN1 1
IN1
GATE1
OUT
GATE2
IN2
VDSFLT
GND
1
2
3
4
5
6
7
15
14 MON1
13
PWRFLT1
12
FUSEFLT1
11
FUSEFLT2
10
PWRFLT2
9 MON2
8 SET
IN1
GATE1
NC
OUT
NC
GATE2
IN2
VDSFLT
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
GND
GATE1 2
NC 3
OUT 4
NC 5
GATE2 6
IN2 7
NC 8
TOP VIEW
16 MON1
15
PWRFLT1
14
FUSEFLT1
13
FUSEFLT2
12
PWRFLT2
11 MON2
10 SET
9
GND
DE14 PACKAGE
14-LEAD (4mm 3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 15) PCB GND CONNECTION OPTIONAL
MS PACKAGE
16-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 125°C/W
S PACKAGE
16-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 75°C/W
ORDER INFORMATION
LEAD FREE FINISH
LTC4355CDE#PBF
LTC4355IDE#PBF
LTC4355CS#PBF
LTC4355IS#PBF
LTC4355CMS#PBF
LTC4355IMS#PBF
TAPE AND REEL
LTC4355CDE#TRPBF
LTC4355IDE#TRPBF
LTC4355CS#TRPBF
LTC4355IS#TRPBF
LTC4355CMS#TRPBF
LTC4355IMS#TRPBF
PART MARKING*
4355
4355
LTC4355CS
LTC4355IS
4355
4355
PACKAGE DESCRIPTION
14-Lead (4mm
×
3mm) Plastic DFN
14-Lead (4mm
×
3mm) Plastic DFN
16-Lead Plastic SO
16-Lead Plastic SO
16-Lead Plastic MSOP
16-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4355fe
2
LTC4355
ELECTRICAL CHARACTERISTICS
SYMBOL
V
OUT
I
OUT
I
INx
ΔV
GATEx
I
GATEx(UP)
I
GATEx(DN)
t
OFF
V
MONx(TH)
V
MONx(HYST)
I
MONx(IN)
V
INx(TH)
V
INx(HYST)
ΔV
SD
ΔV
SD(FLT)
ΔV
SD(FLT)(HYST)
V
FLT
I
FLT
R
SET(L)
R
SET(M)
R
SET(H)
PARAMETER
Operating Supply Range
Supply Current
INx Pin Input Current
External N-Channel Gate Drive
(V
GATEx
– V
INx
)
External N-Channel Gate Pull-Up Current
External N-Channel Gate Pull-Down in Fault
Condition
Gate Turn-Off Time
MONx Pin Threshold Voltage
MONx Pin Hysteresis Voltage
MONx Pin Input Current
INx Pin Threshold Voltage
INx Pin Hysteresis Voltage
Source-Drain Regulation Voltage
(V
INx
– V
OUT )
Short-Circuit Fault Voltage
(V
INx
– V
OUT
) Rising
Short-Circuit Fault Hysteresis Voltage
PWRFLTx, FUSEFLTx, VDSFLT
Pins
Output Low
PWRFLTx, FUSEFLTx, VDSFLT
Pins
Leakage Current
SET Resistance Range for
ΔV
SD(FLT)
= 0.25V
SET Resistance Range for
ΔV
SD(FLT)
= 0.5V
SET Resistance Range for
ΔV
SD(FLT)
= 1.5V
I
PWRFLTx
, I
FUSEFLTx
, I
VDSFLT
= 5mA
V
PWRFLTx
, V
FUSEFLTx
, V
VDSFLT
= 5V
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. 9V < V
OUT
< 80V, unless otherwise noted.
CONDITIONS
l
l
l
l
l
l
l
l
l
l
MIN
9
TYP
2
MAX
80
3
1.2
18
18
–26
UNITS
V
mA
mA
V
V
μA
A
GATE High
V
OUT
= 20V to 80V
V
OUT
= 9V to 20V
V
GATEx
= V
INx
,
V
INx
– V
OUT
= 100mV
Gate Drive Off, V
GATEx
= V
INx
+5V
–
V
INx
– V
OUT
= 55mV |
–
–1V, C
GATE
= 0
V
GATEx
– V
INx
< 1V
0.5
10
4.5
–14
1
0.6
14
6
–20
2
0.3
0.4
1.245
45
±1
4
150
55
0.3
0.6
1.6
200
±1
5
150
μs
V
mV
μA
V
mV
mV
V
V
V
mV
mV
μA
kΩ
kΩ
MΩ
V
MONx
Rising
V
MONx
= 1.23V
V
INx
Rising
V
GATEx
– V
INx
= 2.5V
SET = 0V
SET = 100kΩ
SET = Hi-Z
1.209
10
3
25
10
0.2
0.4
1.3
1.227
30
0
3.5
75
25
0.25
0.5
1.5
30
100
0
l
l
l
l
l
l
l
0
50
1
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3:
The GATEx pins are internally limited to a minimum of 13V above
INx. Driving these pins beyond the clamp may damage the part.
4355fe
3
LTC4355
TYPICAL PERFORMANCE CHARACTERISTICS
I
OUT
vs V
OUT
2.0
V
OUT
= V
IN
1.0
I
IN
vs V
IN
V
IN
= V
OUT
20
I
GATE
vs
Δ
V
SD
V
GATE
= 2.5V
1.5
I
OUT
(mA)
0.75
I
GATE
(μA)
0
I
IN
(mA)
1.0
0.5
–20
0.5
0.25
–40
0
0
20
40
V
OUT
(V)
60
80
4355 G01
0
0
20
40
V
IN
(V)
60
80
4355 G02
–60
–50
0
50
V
SD
(mV)
100
150
4355 G03
Δ
V
GATE
vs I
GATE
15
V
IN
> 18V
0.3
Fault Output Low
vs Load Current
150
Fault Output Low
vs Temperature
I
FLT
= 5mA
125
10
V
GATE
(V)
V
FLT
(V)
V
IN
= 12V
V
IN
= 9V
5
0.2
V
FLT
(V)
0.1
75
0
0
5
10
15
I
GATE
(μA)
20
25
4355 G04
100
0
0
5
I
FLT
(mA)
10
15
4355 G05
50
–50
50
0
TEMPERATURE (°C)
100
4355 G06
FET Turn-Off Time
vs GATE Capacitance
500
V
GATE
< V
IN
+ 1V
V
SD
= 50mV –1V
500
FET Turn-Off Time
vs Initial Overdrive
V
IN
= 48V
V
SD
= V
INITIAL
–1V
2000
FET Turn-Off Time
vs Final Overdrive
V
IN
= 48V
V
SD
= 50mV V
FINAL
400
400
1500
t
OFF
(ns)
t
PD
(ns)
t
PD
(ns)
0
0.2
0.6
0.4
V
INITIAL
(V)
0.8
1.0
4355 G08
300
300
1000
200
200
100
100
500
0
0
10
20
20
C
GATE
(nF)
40
50
4355 G07
0
0
–1.0
–0.8
–0.4
–0.6
V
FINAL
(V)
–0.2
0
4355 G09
4355fe
4
LTC4355
PIN FUNCTIONS
Exposed Pad:
Exposed pad may be left open or connected
to GND.
FUSEFLTx:
Fuse Fault Outputs. Open-drain output that
pulls to GND when V
INx
< 3.5V, indicating that the fuse
has blown open. Otherwise, this output is high impedance.
Connect to GND if unused.
GATEx:
Gate Drive Outputs. The GATE pins pull high,
enhancing the N-channel MOSFET when the load cur-
rent creates more than 25mV of voltage drop across
the MOSFET. When the load current is small, the
gates are actively driven to maintain 25mV across the
MOSFET. If the reverse current develops more than
–25mV of voltage drop across a MOSFET, a fast pull-down
circuit quickly connects the GATE pin to the IN pin, turning
off the MOSFET. Limit the capacitance between the GATE
and IN pins to less than 0.1μF.
GND:
Device Ground.
INx:
Input Voltages and GATE Fast Pull-Down Returns. The
IN pins are the anodes of the ideal diodes and connect to the
sources of the N-channel MOSFETs. The voltages sensed
at these pins are used to control the source-drain voltages
across the MOSFETs and are used by the fault detection
circuits that drive the
PWRFLT, FUSEFLT,
and
VDSFLT
pins.
The GATE fast pull-down current is returned through the IN
pins. Connect these pins as close to the MOSFET sources
as possible. Connect to OUT if unused.
MONx:
Input Supply Monitors. These pins are used to
sense the input supply voltages. Connect these pins to
external resistive dividers between the input supplies and
GND. If V
MONx
falls below 1.23V, the
PWRFLTx
pin pulls
to GND. Connect to GND if unused.
NC:
No Connection. Not internally connected. These
pins provide extra distance between high and low volt-
age pins.
OUT:
Drain Voltage Sense and Positive Supply Input. OUT
is the diode-OR output of IN1 and IN2. It connects to the
common drain connection of the N-channel MOSFETs. The
voltage sensed at this pin is used to control the source-
drain voltages across the MOSFETs and is used by the
fault detection circuits that drive the
PWRFLT
and
VDSFLT
pins. The LTC4355 is powered from the OUT pin.
PWRFLTx:
Power Fault Outputs. Open-drain output
that pulls to GND when V
MONx
falls below 1.23V or
the forward voltage across the MOSFET exceeds
ΔV
SD(FLT)
. When V
MONx
is above 1.23V and the
forward voltage across the MOSFET is less than
ΔV
SD(FLT)
,
PWRFLTx
is high impedance. Connect to GND
if unused.
SET:
ΔV
SD(FLT)
Threshold Configuration Input. Tying SET
to GND, to a 100k resistor connected to GND, or leaving
SET open configures the
ΔV
SD(FLT)
forward voltage fault
threshold to 250mV, 500mV, or 1.5V, respectively. When the
voltage across a MOSFET exceeds
ΔV
SD(FLT)
, the
VSDFLT
pin and at least one of the
PWRFLT
pins pull to GND.
VDSFLT:
MOSFET Fault Output. Open-drain output that
pulls to GND when the forward voltage across either
MOSFET exceeds
ΔV
SD(FLT)
.
PWRFLT1
or
PWRFLT2
also
pulls low to indicate which MOSFET’s forward voltage drop
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
