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MPC8323CZQAFDCA: 产品描述32-BIT, 333 MHz, RISC PROCESSOR, PBGA516; 产品类别半导体嵌入式处理器和控制器; 文件大小947KB，共82页; 制造商FREESCALE (NXP)

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MPC8323CZQAFDCA概述

32-BIT, 333 MHz, RISC PROCESSOR, PBGA516

32位, 333 MHz, RISC处理器, PBGA516

MPC8323CZQAFDCA规格参数

参数名称	属性值
功能数量	1
端子数量	516
最大供电/工作电压	1.05 V
最小供电/工作电压	0.9500 V
额定供电电压	1 V
外部数据总线宽度	0.0
线速度	333 MHz
加工封装描述	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
状态	ACTIVE
包装形状	SQUARE
包装尺寸	GRID ARRAY
表面贴装	Yes
端子形式	BALL
端子间距	1 mm
端子涂层	TIN LEAD SILVER
端子位置	BOTTOM
包装材料	PLASTIC/EPOXY
地址总线宽度	0.0
位数	32
边界扫描	Yes
最大FCLK时钟频率	66.67 MHz
浮点运算单元	Yes
集成缓存	Yes
低功耗模式	Yes
微处理器类型	RISC PROCESSOR

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Freescale Semiconductor

Technical Data

Document Number: MPC8323EEC

Rev. 3, 02/2010

MPC8323E

PowerQUICC™ II Pro Integrated

Communications Processor

Family Hardware Specifications

This document provides an overview of the MPC8323E

PowerQUICC™ II Pro processor features. The MPC8323E

is a cost-effective, highly integrated communications

processor that addresses the requirements of several

networking applications, including ADSL SOHO and

residential gateways, modem/routers, industrial control, and

test and measurement applications. The MPC8323E extends

current PowerQUICC offerings, adding higher CPU

performance, additional functionality, and faster interfaces,

while addressing the requirements related to time-to-market,

price, power consumption, and board real estate. This

document describes the MPC8323E, and unless otherwise

noted, the information also applies to the MPC8323,

MPC8321E, and MPC8321.

To locate published errata or updates for this document, refer

to the MPC8323E product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ethernet and MII Management . . . . . . . . . . . . . . . . . 19

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

HDLC, BISYNC, Transparent, and Synchronous

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

System Design Information . . . . . . . . . . . . . . . . . . . 76

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79

Document Revision History . . . . . . . . . . . . . . . . . . . 80

Overview

NOTE

The QUICC Engine block can also support a UTOPIA level 2 capable of

supporting 31 multi-PHY (MPC8323E- and MPC8323-specific).

The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded

from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,

3DES, AES, SHA-1, and MD-5 algorithms.

In summary, the MPC8323E family provides users with a highly integrated, fully programmable

communications processor. This helps ensure that a low-cost system solution can be quickly developed

and offers flexibility to accommodate new standards and evolving system requirements.

1.1

MPC8323E Features

Major features of the MPC8323E are as follows:

• High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for

ATM or IP/Ethernet packet processing (or both).

• MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by

supporting programmable protocol termination and network interface termination to meet evolving

protocol standards.

• Single platform architecture supports the convergence of IP packet networks and ATM networks.

• DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1

and DDR2.

• An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches,

and dual integer units.

• Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus

interface up to 66-MHz operation, and USB 2.0 (full-/low-speed).

• Security engine provides acceleration for control and data plane security protocols.

• High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration.

1.1.1

Protocols

The protocols are as follows:

• ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1)

• Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0)

• Support for IMA and ATM transmission convergence sub-layer

• ATM OAM handling features compatible with ITU-T I.610

• IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum

processing

• Extensive support for ATM statistics and Ethernet RMON/MIB statistics

• Support for 64 channels of HDLC/transparent

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

1.1.2

Serial Interfaces

The MPC8323E serial interfaces are as follows:

• Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only)

• Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII

• Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM)

• Support for dual UART and SPI interfaces and a single I

C interface

1.2

QUICC Engine Block

The QUICC Engine block is a versatile communications complex that integrates several communications

peripheral controllers. It provides on-chip system design for a variety of applications, particularly in

communications and networking systems. The QUICC Engine block has the following features:

• One 32-bit RISC controller for flexible support of the communications peripherals

• Serial DMA channel for receive and transmit on all serial channels

• Five universal communication controllers (UCCs) supporting the following protocols and

interfaces (not all of them simultaneously):

— 10/100 Mbps Ethernet/IEEE 802.3® standard

— IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing

— ATM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not

support the UTOPIA interface)

— HDLC /transparent up to 70-Mbps full-duplex

— HDLC bus up to 10 Mbps

— Asynchronous HDLC

— UART

— BISYNC up to 2 Mbps

— QUICC multi-channel controller (QMC) for 64 TDM channels

• One UTOPIA interface (UPC1) supporting 31 multi-PHYs (MPC8323E- and MPC8323-specific)

• Two serial peripheral interfaces (SPI). SPI2 is dedicated to Ethernet PHY management.

• Four TDM interfaces

• Thirteen independent baud rate generators and 19 input clock pins for supplying clocks to UCC

serial channels

• Four independent 16-bit timers that can be interconnected as two 32-bit timers

The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and

FCC (fast Ethernet, HDLC, transparent, and ATM).

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

MPC8323CZQAFDCA相似产品对比

	MPC8323CZQAFDCA	MPC8323ECZQAFDCA	MPC8323EEC	MPC8323EZQAFDCA	MPC8323E_10
描述	32-BIT, 333 MHz, RISC PROCESSOR, PBGA516	32-BIT, 333 MHz, RISC PROCESSOR, PBGA516	32-BIT, 333 MHz, RISC PROCESSOR, PBGA516	32-BIT, 333 MHz, RISC PROCESSOR, PBGA516	32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
功能数量	1	1	1	1	1
端子数量	516	516	516	516	516
最大供电/工作电压	1.05 V	1.05 V	1.05 V	1.05 V	1.05 V
最小供电/工作电压	0.9500 V	0.9500 V	0.9500 V	0.9500 V	0.9500 V
额定供电电压	1 V	1 V	1 V	1 V	1 V
外部数据总线宽度	0.0	0.0	0.0	0.0	0.0
线速度	333 MHz	333 MHz	333 MHz	333 MHz	333 MHz
加工封装描述	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
状态	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE
包装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
包装尺寸	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
表面贴装	Yes	Yes	Yes	Yes	Yes
端子形式	BALL	BALL	BALL	BALL	BALL
端子间距	1 mm	1 mm	1 mm	1 mm	1 mm
端子涂层	TIN LEAD SILVER	TIN LEAD SILVER	TIN LEAD SILVER	TIN LEAD SILVER	TIN LEAD SILVER
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
包装材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
地址总线宽度	0.0	0.0	0.0	0.0	0.0
位数	32	32	32	32	32
边界扫描	Yes	Yes	Yes	Yes	Yes
最大FCLK时钟频率	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz
浮点运算单元	Yes	Yes	Yes	Yes	Yes
集成缓存	Yes	Yes	Yes	Yes	Yes
低功耗模式	Yes	Yes	Yes	Yes	Yes
微处理器类型	RISC PROCESSOR	RISC PROCESSOR	RISC PROCESSOR	RISC PROCESSOR	RISC PROCESSOR

MPC8323CZQAFDCA

MPC8323CZQAFDCA概述

MPC8323CZQAFDCA规格参数

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