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HMP31GF7EMR4C-S5: 产品描述240pin Fully Buffered DDR2 SDRAM DIMMs; 产品类别存储存储; 文件大小1MB，共32页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/; 标准

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HMP31GF7EMR4C-S5概述

240pin Fully Buffered DDR2 SDRAM DIMMs

HMP31GF7EMR4C-S5规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
针数	240
Reach Compliance Code	compli
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
其他特性	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
JESD-30 代码	R-XZMA-N203
长度	133.35 mm
内存密度	8589934592 bi
内存集成电路类型	DDR DRAM MODULE
内存宽度	8
功能数量	1
端口数量	1
端子数量	240
字数	1073741824 words
字数代码	1000000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度
组织	1GX8
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	30.35 mm
自我刷新	YES
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	NO
技术	CMOS
温度等级	OTHER
端子形式	NO LEAD
端子位置	ZIG-ZAG
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	8.2 mm

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240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver.

This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow

host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that

isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of

each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the

host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host

controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point

Link Interface at 1.5V power.

The AMB also allows buffering of memory traffic to support large memory capacities. All memory control

for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,

scrubbing, sparing, configuration access and power management. The AMB interface is responsible for

handling channel and memory requests to and from the local FBDIMM and for forwarding request to other

FBDIMMs on the memory channel.

FEATURES

•

240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module

JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

All inputs and outputs are compatible with SSTL_1.8 interface

Built with 1Gb DDR2 SDRAMs in 60ball FBGA

Host interface and AMB component industry standard compliant

MBIST, IBIST test functions

8 Bank architecture

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

133.35 x 30.35 mm form factor

RoHS compliant

Full DIMM Heat Spreader

This document is a general product description and is subject to change without notice. Hynix Electronics does not

assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Sep. 2008

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