200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP)
This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR
SDRAMs in 400 mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 256Mb D ver. based unbuffered
SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
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•
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JEDEC Standard 200-pin small outline, dual in-line
memory module (SO-DIMM)
Two ranks 32M x 64 and One rank 32M x 64, 16M x
64 organization
2.6V
±
0.1V VDD and VDDQ Power supply for
DDR400, 2.5V
±
0.2V for DDR333 and below
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
133/166/200MHz
DLL aligns DQ and DQS transition with CK transition
Programmable CAS Latency: DDR266(2, 2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
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Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial Presence Detect (SPD) with EEPROM
Built with 256Mb DDR SDRAMs in 400 mil TSOP II
packages
Lead-free product listed for each configuration
(RoHS compliant)
ADDRESS TABLE
Organization
256MB
256MB
128MB
32M x 64
32M x 64
16M x 64
Ranks
2
1
1
SDRAMs
16Mb x 16
32Mb x 8
16Mb x 16
# of
DRAMs
8
8
4
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/9(A0~A8)
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
13(A0~A12)/2(BA0,BA1)/9(A0~A8)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
PERFORMANCE RANGE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
CL=3
Max Clock
Frequency
CL=2.5
CL=2
-D43
1
DDR400B
3-3-3
200
166
133
-J
DDR333
2.5-3-3
-
166
133
-K
DDR266A
2-3-3
-
133
133
-H
DDR266B
2.5-3-3
-
133
133
Unit
-
CK
MHz
MHz
MHz
Note:
1. 2.6V +/- 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V +/- 0.2V for DDR333 and below
Rev. 1.1 / May. 2005
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
11
200pin Unbuffered DDR SDRAM SO-DIMMs
ORDERING INFORMATION
Part Number
HYMD216M646D[L]6-D43/J/K/H
HYMD216M646D[L]P6-D43/J/K/H
HYMD232M646D[L]8-D43/J/K/H
HYMD232M646D[L]P8-D43/J/K/H
HYMD232M646D[L]6-D43/J/K/H
HYMD232M646D[L]P6-D43/J/K/H
Density
128MB
128MB
256MB
256MB
256MB
256MB
Organization Ranks
16M x 64
16M x 64
32M x 64
32M x 64
32M x 64
32M x 64
1
1
1
1
2
2
# of
DRAMs
4
4
8
8
8
8
Material
Normal
Lead-free
1
Normal
Lead-free
1
Normal
Lead-free
1
DIMM Dimension
67.60 x 31.75 x 3.8 [mm
3
]
↑
↑
↑
↑
↑
Note:
1. The “Pb-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.
* These products are built with HY5DU564(8,16)22DT[L][P] the Hynix DDR SDRAM component.
Rev. 1.1 / May. 2005
2
11
200pin Unbuffered DDR SDRAM SO-DIMMs
PIN DESCRIPTION
Pin
CK0~2, /CK0~2
/CS0, /CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A13
A10/AP
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~8
Pin Description
Differential Clock Inputs
Chip Select Inputs
Clock Enable Inputs
Commend Sets Inputs
Address Inputs
Address Input/Autoprecharge
Bank Address
Data Inputs/Outputs
Data Check bits
Data Strobes
Data-in Masks
Pin
VDD
VSS
VREF
VDDSPD
VDDID
SA0~SA2
SCL
SDA
DU
NC
TEST
Pin Description
Power Supply for Core and I/O
Ground
Input/Output Reference
Power Supply for SPD
VDD, VDDQ Level Detection
SPD Address Inputs
SPD Clock Input
SPD Data Input/Output
Do not Use
No Connection
Reserved for test equipment use
PIN ASSIGNMENT
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Name
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Name
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Name
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
/CK2
VDD
CKE1
DU
A12
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Name
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU
VSS
VSS
VDD
VDD
CKE0
DU
A11
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Name
A9
VSS
A7
A5
A3
A1
VDD
A10,AP
BA0
/WE
/CS0
NC,A13
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Name
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Name
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Name
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
NC,TEST
note:
1. Pins 71, 72, 73, 74,77,78,79, 80, 83, 84 are reserved for x72 variants of this module and are not used on the x64 versions.
2. Pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version.
3. Pin 89, 91 are reserved for x72 modules or registered modules and is not used on the unbuffered version.
4. Pin 95, 122 are not used for single rank module.
5. Pin 123 is “NC” for 256MB, 512MB, and 1GB, or “A13” for 2GB module.
Rev. 1.1 / May. 2005
3
11
200pin Unbuffered DDR SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
128MB, 16M x 64 Unbuffered SO-DIMM: HYMD216M646D[L][P]6
/CS
DQS0
DM0
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQS1
DM1
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
/CS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
D0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
/CS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
D2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
LDQS
LDM
/S
LDQS
LDM
/S
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
D1
D3
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
# Unless otherwise noted, resistor values are 22O +- 5%
BA0-BA1
A0-AN
/RAS
/CAS
/WE
SDRAMs D0-D3
SDRAMs D0-D3
SDRAMs D0-D3
SDRAMs D0-D3
SDRAMs D0-D3
Serial Presence Detector
(SPD)
CK0
/CK0
CK1
/CK1
CK2
/CK2
2 loads
SCL
SA0
SA1
SA2
A0
A1
A2
2 loads
0 loads
SDA
WP
CKE0
CKE1
VDD SPD
VREF
VDD
VSS
VDDID
SDRAMs D0-D3
N.C.
SPD
SDRAMS DO-D7
SDRAMS DO-D7
VDD and VDDQ
SDRAMS DO-D7,SPD
Strap:see Note 4
Notes :
DQ wiring may differ from that described in this
drawing : however DQ/DM/DQS relationship are
maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open) : VDD = VDDQ
Strap in (closed) : VDD
≠
VDDQ
Rev. 1.1 / May. 2005
4
11
200pin Unbuffered DDR SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]8
/CS
DQS0
DM0
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D0
DQS1
DM1
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D1
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D4
/CS
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D2
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D3
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
D6
/CS
D7
# Unless otherwise noted, resistor values are 22O +- 5%
BA0-BA1
A0-AN
/RAS
/CAS
SDRAMs D0-D7
SDRAMs D0-D7
SDRAMs D0-D7
SDRAMs D0-D7
SCL
Serial Presence Detector
(SPD)
CK0
/CK0
4 loads
SA0
SA1
SA2
A0
A1
A2
WP
/WE
CKE0
CKE1
SDRAMs D0-D7
SDRAMs D0-D3
N.C.
SDA
CK1
/CK1
CK2
/CK2
4 loads
0 loads
VDD SPD
VREF
VDD
VSS
VDDID
SPD
SDRAMS DO-D7
SDRAMS DO-D7
VDD and VDDQ
SDRAMS DO-D7,SPD
Strap:see Note 4
Notes :
DQ wiring may differ from that described in this
drawing : however DQ/DM/DQS relationship are
maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open) : VDD = VDDQ
Strap in (closed) : VDD
≠
VDDQ
Rev. 1.1 / May. 2005
5
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