A3948
DMOS Full-Bridge PWM Motor Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: April 28, 2007
Recommended Substitutions:
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
3948
A3948SLB
(SOIC)
CP
CP
2
CP
1
PHASE
OSC
GROUND
GROUND
LOGIC SUPPLY
ENABLE
DATA
CLOCK
STROBE
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
1
2
3
4
5
θ
24
23
NC
22
21
V
BB
20
19
18
V
DD
17
16
V
REG
RANGE
NO
CONNECTION
OUT
B
LOAD SUPPLY
GROUND
GROUND
SENSE
OUT
A
NO
CONNECTION
MODE
REF
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3948SB and A3948SLB are capable of continuous output
currents to
±1.5
A and operating voltages to 50 V. Internal fixed off-
time PWM current-control timing circuitry can be programmed via a
serial interface to operate in slow, fast, and mixed current-decay
modes. Similar devices with outputs rated to
±2
A are available as the
A3958SB/SLB.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. The ENABLE input can be
programmed via the serial port to PWM the bridge in fast or slow
current decay. Internal synchronous rectification control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover-current protection. Special power-up
sequencing is not required.
The A3948SB/SLB is supplied in a choice of two power
packages, a 24-pin plastic DIP with a copper batwing tab (package
suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab
(package suffix ‘LB’). In both cases, the power tab is at ground
potential and needs no electrical isolation.
Data Sheet
29319.36A
6
7
8
9
9
LOGIC
CHARGE PUMP
SERIAL PORT
10
11
12
NC
15
14
÷
13
Dwg. PP-069A
Note that the A3948SLB(SOIC) and A3948SB
(DIP) do not share a common terminal
assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
..................
50 V
Output Current, I
OUT
........................
±
1.5 A
Logic Supply Voltage, V
DD
................
7.0 V
Input Voltage, V
IN
....
-0.3 V to V
DD
+ 0.3 V
Sense Voltage, V
S
..........................
0.55 V
Reference Voltage, V
REF
..................
5.5 V
Package Power Dissipation (T
A
= 25°C), P
D
A3948SB .................................
3.1 W*
A3948SLB ...............................
1.6 W*
Operating Temperature Range,
T
A
...............................
-20
°
C to +85
°
C
Junction Temperature,
T
J
............................................
+150
°
C
Storage Temperature Range,
T
S
.............................
-55
°
C to +150
°
C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
* Per SEMI G42-88 Specification.
FEATURES
s
s
s
s
s
s
s
±1.5
A, 50 V Continuous Output Rating
Low
r
DS(on)
Outputs
Programmable Mixed, Fast, and Slow Current-Decay Modes
Serial Interface Controls Chip Functions
Synchronous Rectification for Low Power Dissipation
Internal UVLO and Thermal-Shutdown Circuitry
Crossover-Current Protection
Always order by complete part number:
Part Number
A3948SB
A3948SLB
Package
24-pin batwing DIP
24-lead batwing SOIC
R
θ
JA
40°C/W
77°C/W
R
θ
JT
6°C/W
6°C/W
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Load Supply Current
V
BB
I
DSS
r
DS(on)
V
F
I
BB
Operating
During sleep mode
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= -1.5 A
Sink driver, I
OUT
= 1.5 A
Source diode, I
F
= -1.5 A
Sink diode, I
F
= 1.5 A
f
PWM
< 50 kHz
Charge pump on, outputs disabled
Sleep Mode
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
(all inputs except ENABLE)
ENABLE Input Current
OSC input frequency
OSC input duty cycle
OSC input hysteresis
Input Hysterisis
Reference Input Volt. Range
Reference Input Current
Comparator Input Offset Volt.
V
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
I
IN(1)
I
IN(0)
f
OSC
dc
OSC
–
–
V
REF
I
REF
V
IO
V
IN
= 2.0 V
V
IN
= 0.8 V
V
IN
= 2.0 V
V
IN
= 0.8 V
Operating
Operating
Operating
All digital inputs except OSC
Operating
V
REF
= 2.5 V
V
REF
= 0 V
Operating
4.5
2.0
–
–
–
–
–
1.8
40
200
50
0.0
–
–
5.0
–
–
<1.0
<-2.0
40
16
–
–
–
–
–
–
0
5.5
–
0.8
20
-20
100
40
6.1
60
400
100
V
DD
- 0.1
±0.5
±5.0
V
V
V
µA
µA
µA
µA
MHz
%
mV
mV
V
µA
mV
20
0
–
–
–
–
–
–
–
–
–
–
–
<1.0
<-1.0
500
300
1.0
1.0
4.0
2.0
–
50
50
20
-20
550
350
1.3
1.3
7.0
5.0
20
V
V
µA
µA
mΩ
mΩ
V
V
mA
mA
µA
Symbol Test Conditions
Min. Typ. Max.
Units
Continued next page …
www.allegromicro.com
3
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise), continued.
Limits
Characteristics
Control Logic
Buffer Input Offset Volt.
Reference Divider Ratio
Propagation Delay Times
V
IO
–
t
pd
D14 = High
D14 = Low
PWM change to source ON
PWM change to source OFF
PWM change to sink ON
PWM change to sink OFF
Phase change to sink ON
Phase change to sink OFF
Phase change to source ON
Phase change to source OFF
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
T
J
∆T
J
UVLO
∆UVLO
I
DD
f
PWM
< 50 kHz
Sleep Mode, Inputs < 0.5 V
Increasing V
DD
–
9.9
4.95
–
–
–
–
–
–
–
–
–
–
3.90
0.05
–
–
0
10
5.0
600
100
600
100
600
100
600
100
165
15
4.2
0.10
6.0
–
±15
10.2
5.05
–
–
–
–
–
–
–
–
–
–
4.45
–
10
2.0
mV
–
–
ns
ns
ns
ns
ns
ns
ns
ns
°C
°C
V
V
mA
mA
Symbol Test Conditions
Min. Typ. Max.
Units
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
4
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