Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
1 Features
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PDH Interfaces
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Versatile IC supports 622 Mbits/s/155 Mbits/s
SONET/SDH interface solutions for T3/E3, DS2,
T1/E1/J1, and DS0/E0/J0 applications.
Implementation supports both linear (1 + 1, unpro-
tected) and ring (UPSR) network topologies.
Provides full termination of up to 63 (21 x 3) E1,
84 (28 x 3) T1, or 84 (28 x 3) J1.
Low 3.3 V power supply.
–40
°C
to +85 °C industrial temperature range.
700-pin ball grid array (PBGA) package.
Complies with
Telecordia Technologies*,
ITU,
ANSI
†
, ETSI, and Japanese TTC standards: GR-
253-CORE, GR-499, (ATT) TR-62411, ITU-T
G.707, G.704, G.706, G.783, G.962, G.964,
G.965, Q.542, T1.105, JT-G704, JT-G706, JT-
G707, JT-I431-a, ETS 300 417-1-1, ETS 300 011,
T1.107, T1.404.
6
DS3, 21 x DS2,
or 6 E3,
12 x E2.
Twenty-one framed or unframed DS1 or E1 inter-
faces.
Two additional protection
channels for DS2/DS1/
E1.
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STS/STM Pointer Interpreter
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Interprets STS/AU/TU-3 pointers.
Synchronizes 8 kHz frame and 2 kHz superframe
to system-shelf-timing reference by setting the
transmit STS-3/STM-1 pointers to a fixed value
of 522
with an adjustable frame location.
Monitors/terminates SPE path overhead.
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STS3 Serial Interconnect
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SONET/SDH Interface
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Serial interface to mate devices.
4 Ultramapper devices, 3 configured as mate
devices, provide full termination of an STS-12/
STM-4. A 4 chip solution to terminate
336 DS1s/J1s or 252 E1s.
Termination of a single 622 Mbits/s STS-12/STM-4
or single 155 Mbits/s STS-3/STM-1.
Built-in clock and data recovery circuit at
622 Mbits/s STS-12/STM-4 interface.
Supports overhead processing for all transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel.
Configurable as dedicated DCC channels.
Software controlled linear 1 + 1 protection via dedi-
cated interface to protection card.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm
reporting.
Built-in diagnostic loopback modes.
8 kHz line frame synchronizing output.
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VT Termination/Generation 84/63 (3x28/21)
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Supports TIM-V generation and termination for all
84/63 (3x28/21) VT/TU signals.
Synchronizes VT/TU SPE to system-shelf-timing
reference by setting the transmit VT/TU pointers to
fixed values for asynchronous mapping or by
dynamically changing the transmit VT/TU pointers
for byte synchronous mapping.
Fixed pointer generation in transmit side for asyn-
chronous mapping.
Dynamic pointer generation in transmit side for
byte-synchronous mapping.
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*
Telecordia Technologies
is a trademark of Telecordia Technolo-
gies Inc.
†
ANSI
is a registered trademark of American National Standards
Institute, Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
E13 Features (3)
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Features
(continued)
Mapping/Multiplexing Modes 84/63 (3x28/21)
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Configurable multiplexer/demultiplexer for up to
16 E1 signals, or 4 E2 signals to/from an E3 signal.
Independently configurable 4 E12 multiplexer/demul-
tiplexers for up to 16 E1 signals to/from 4 E2 signals.
Provisionable time-slot selection for E1, E2 insertion,
or drop via the cross connect macro.
E12 multiplexers capable of generating alarm indica-
tion signal (AIS) and remote alarm indicator (RAI)
signals.
E23 multiplexer capable of generating AIS and RAI
signals.
Configurable HDB3 encoder/decoder for E3 output/
input.
E1 and E2 transmit path monitors that detect loss of
clock (LOC) and AIS.
E2 receive path monitor that detects LOC, AIS, and
RAI.
E3 receive monitor that detects loss of signal (LOS),
LOC, bipolar violation (BPV), AIS, and RAI.
E3 and E2 loopback modes.
Complies with ITU’s G.703, G.742, G.751, and
G.775.
Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
Maps T1/E1/J1
into
VT/TU structures.
Maps T1
into
VT1.5/TU-11/TU-12.
Maps J1
into
VT1.5/TU-11/TU-12.
Maps E1
into
VT2/TU-12.
Supports asynchronous, byte-synchronous, and bit-
synchronous mapping.
Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1.
STS-3/STS-1/SPE/VTG/VTx.
STM-1/AU-3/TUG-2/TU-1x/VC-1x.
STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x.
Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
Supports J2 trace identifier monitoring/insertion.
Configurable VT/TU slot selection for DS1, E1, J1
insertion and drop.
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
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DS3/DS2/DS1/E1 Cross Connect Features
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M13 Features (3)
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Configurable crosspoint interconnect for up to 28 x 3
DS1 signals or 21 x 3 E1 signals to/from the framer,
30 external pins, and 28 x 3 signal channels to/from
the M13 and VT mapper. Also supports up to 7 x 3
DS2 signals to/from the external pins or M12 MUXes,
connecting to the M13 MUX M23 block.
Connects six clear channel DS3, E3, and STS-1 sig-
nals from the external pins to the M13, E13,
SPE_mapper, and STS1-LT.
Also connects three unchannelized DS3 and E3 sig-
nal to/from the external NSMI interface to the SPE,
M13, E13, framer, or TPG blocks.
The three NSMI
pins can also be shared for STS-1
LT.
Any mix of 168 DS1, E1 signals may be intercon-
nected. Any of the available DS1/E1 signal sources
may be connected to any of 168 signal destinations
in the DS1/E1 cross connect. Multicast or broadcast
operation (one port to many) is supported for up to
168 channels. Also, any channel n at the source can
be connected to its corresponding destination chan-
nel n, where n ranges from 1 to 84 for most sources
and destinations.
Agere Systems Inc.
Configurable multiplexer/demultiplexer for
28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/
from a DS3 signal.
Operates in either M23 or C-bit parity mode.
Provisionable time-slot selection for DS1, E1, and
DS2 insertion or drop.
Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-
ity errors, FEBE).
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
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2
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
DS3/E3 Digital Jitter Attenuation Features
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Features
(continued)
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Any mix of DS2, DS3, or E3 signals may be intercon-
nected.
Cross connect allows 16 x 3 E1 signals to/from E13
modules to framer, M13, VT mapper, and external
pins.
There are 4 x 3 E2 signals to/from E13 to external
pins, TPG generator/monitor.
There are 3 E3 signals to/from the E13 block to
external pins, TPG generator/monitor, and SPE map-
per.
Jitter attenuation may also be inserted in-line on any
DS1/E1 channel. (Note that cascading of jitter atten-
uators is not allowed.)
Standard network loopback or straightaway facility
testing is supported for DS1/E1 and DS3/E3. Any
source or transmitter may be replaced by a test-pat-
tern generator capable of injecting idle standards-
based pseudorandom bit sequence test patterns, or
AIS (blue) alarm. Any sink or receiver may be
replaced by a test-pattern monitor, which can detect/
count bit errors in a pseudorandom test sequence, or
loss of frame or loss of synchronization.
One to any loopback is supported for up to
168 channels in DS1/E1 channels in blocks VT map-
per, M13, E13, and framer. One-to-one loopback is
supported in all DS1/E1 channels. One-to-one loop-
back for DS3/E3/STS-1 channels in blocks M13,
E13, and SPE mapper.
Loopbacks may be configured to sectionalize a cir-
cuit for identifying faults or misconfiguration during
out of service maintenance.
Fast alarm channels are supported for VT mapper,
E13, or M13 to framer interconnects for alarm indica-
tion signal (AIS or blue alarm), and VT mapper only
for remote alarm indicator (RAI or yellow alarm). This
feature reduces the propagation delay of the alarms
by eliminating multiple integration of alarm condi-
tions.
Supports framer-only, transport (framer LIU, M13,
E13, and VT mapper), and switching (CHI and PSB)
modes of operation.
TOAC outputs are available in DS1/E1 framed format
at any destination. Any DS1/E1 channel can be used
as TOAC inputs.
The PLL bandwidth, damping factor, and sampling
rates are programmable.
The DJA macro accepts/delivers DS3/E3 clock and
data from/to the cross connect macrocell.
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T1/E1/J1 Framing Features 84/63 (3x28/21)
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28/21 T1/E1/J1 channels.
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
T1 framing modes: ESF, D4,
SLC
®
-96, T1 DM DDS,
and SF (F
t
only).
E1 framing: G.704 basic and CRC-4 multiframe con-
sistent with G.706.
J1 framing modes: JESF (Japan).
Supports T1 and E1 unframed and transparent trans-
mission format.
T1 signaling modes: transparent; register and sys-
tem access for ESF 2-state, 4-state, and 16-state;
D4 2-state, 4-state, and 16-state;
SLC-96
2-state,
4-state, and 16-state; J-ESF handling groups mainte-
nance and signaling; VT 1.5 SPE 2-, 4-, 16-state.
E1 signaling modes: transparent; register and sys-
tem access for entire TS16 multiframe structure as
per ITU G.732.
Signaling debounce and change of state interrupt.
V5.2 Sa7 processing.
Alarm reporting and performance monitoring per
AT&T,
ANSI,
ITU-T, and ETSI standards.
Facility data link features:
— HDLC or transparent access for either ESF or
DDS+ FDL frame formats.
— Register/stack access for
SLC-96
transmit and
receive data.
— Extended superframe (ESF): automatic transmis-
sion of the ESF performance report messages
(PRM). Automatic transmission of the
ANSI
T1.403 ESF performance report messages.
Automatic detection and transmission of the
ANSI
T1.403 ESF FDL bit-oriented codes.
— Register/stack access for all CEPT Sa-bits trans-
mit and receive data.
HDLC features:
— HDLC or transparent mode.
— Programmable logical channel assignment: any
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
— 64 logical channels in both transmit and receive
direction (any framing format).
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DS1/E1 Digital Jitter Attenuation Features
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PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
Configurable to meet jitter and MTIE requirements.
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Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
SPEMPR Features
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Features
(continued)
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
E1 Sa-bit).
— 128-byte FIFO per channel in both transmit and
receive direction.
— Tx to Rx loopback supported.
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The SPE mapper accepts/delivers TUG-2 data from/
to the VT mapper. The TUG-2 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers DS3 data from/to
the M13 MUX/deMUX. The DS3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers a clear DS3 signal
at 44.736 Mbits/s rate. The clear DS3 signal is
mapped/demapped essentially the same way as
M13 signal described above.
The SPE mapper accepts/delivers E3 data from/to
the E13 MUX/deMUX. The E3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers a clear E3 signal
at 34.368 Mbits/s rate. The clear E3 signal is
mapped/demapped essentially the same way as E13
signal described above.
The SPE mapper has a DS3/E3 loopback circuit
placed for the functions of demapping and remap-
ping a DS3/E3 signal. It is particularly useful in cases
where a DS3/E3 signal mapped as an AU-3/STS-1
signal has to be remapped as a TUG-3 signal or vice
versa.
The SPE mapper supports a path overhead access
channel more commonly known as the POAC chan-
nel. Seven path overhead bytes namely J1, C2, F2,
H4, F3, K3, and N1 may be inserted/dropped
through this channel. This channel works as the
master, which means that this channel provides a
clock in both transmit and receive directions and
POH data may be inserted by the user on the trans-
mit side or dropped by the block in the receive side.
Path overhead byte B3 (BIP error) generation/detec-
tion and programmable BIP-8 bit error rate insertion.
Programmable clear on read/clear on write registers.
Signal fail and signal degrade indicators available to
report bit error rates above a certain programmable
threshold.
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System interfaces:
— Concentration highway interface.
— Single clock and frame synchronizing signals;
programmable clock rates at 2.048 MHz,
4.096 MHz, 8.192 MHz, and 16.384 MHz;
programmable data rates at 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s;
programmable clock edges and bit/byte offsets.
— Parallel system bus interface at 19.44 MHz for
data and signaling: single clock and frame syn-
chronizing signals.
— Time-division multiplex data rate serial interface at
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame synchronizing signals.
Twenty-eight transmit data signals with a global
clock and frame synchronization.
— Network serial multiplexed interface
(NSMI)
mini-
mal pin count serial interface at 51.84 MHz opti-
mized for data and IMA applications.
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MPU Features
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21-bit address/16-bit data bus microprocessor inter-
face.
Synchronous (16 MHz to 66 MHz)/asynchronous
microprocessor interface modes.
Microprocessor data bus parity monitoring.
Summary of 2 level priority interrupts from major
functional blocks/maskable.
Separate device interrupt outputs for automatic pro-
tection switch and the Ultramapper global interrupt.
Global configuration of network performance moni-
toring counters operation.
Global software resets.
Global enabling and powering down of major func-
tional blocks.
Miscellaneous global configuration and control.
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4
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the SPE
mapper transmit blocks.
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Features
(continued)
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Capable of detecting/inserting alarm indication sig-
nals (AIS), remote defect indication signals (RDI),
and remote error indication signals (REI).
Numerous monitoring functions provided on all the
TUG-3 path overhead bytes.
Supports unidirectional path switch ring (UPSR)
applications.
N1 tandem connection support is provided.
The TUG3 pointer processor can be used for an add/
drop multiplexer.
Complies with GR-253-CORE, T1.105, ITU-T G.707,
ITU-T G.831, G.783, ETS 300 417-1-1.
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Configurable connection for up to 3 STS1 signals
from 3 STS1LT PP blocks to any 1 up to 3 STS1 slots
of any 1 of 4 TMUX transmit interfaces. Clock and
control signals are provided by the TMUX transmit
interfaces and data is supplied by the STS1LT
receive blocks.
Configurable connection for up to 12 STS1 signals
from the STS12PP transmit block to any 1 up to
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the
STS12PP transmit blocks.
Configurable connection for up to 9 STS1 signals
from 3 CDR receive blocks to any 1 up to 3 STS1
slots of any 1 of 4 TMUX transmit interfaces. Clock
and control signals are provided by the TMUX trans-
mit interfaces and data is supplied by the CDR
receive blocks.
Configurable connection for up to 3 STS1 signals
from 6 SPE mapper transmit blocks to any 1 of
3 STS1LT transmit blocks. Clock and control signals
are provided by the STS1LT transmit block and data
is supplied by the SPE mapper transmit block.
Configurable connection for up to 3 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 STS1LT transmit
blocks. Data is provided by the TMUX receive inter-
faces for this transfer.
Configurable connection for up to 9 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 CDR transmit blocks.
Clock, control signals, and data are provided by the
TMUX receive interfaces for this transfer.
Configurable connection for up to 3 STS1 signals
from 3 STS1LT receive blocks to any 1 of 6 SPE
mapper receive blocks. Clock, control signals, and
data are provided by the STS1LT receive block for
this transfer.
Configurable connection for up to 6 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 6 SPE mapper receive
blocks. Clock, control signals, and data are provided
by the TMUX receive interfaces for this transfer.
Loss of clock detectors on three serial 155 MHz clock
inputs from three CRD RX blocks and one serial
155 MHz clock input from CDR TX block.
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STS12 Pointer Processor Features
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SONET and SDH compliant.
Configurable STS-3/STM-1 or STS-12/STM-4 mode.
Supporting an arbitrary mix of STS-1 and STS3c trib-
utaries, and SDH equivalents.
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
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STS1LT Features
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Supports standard SPE mappings for sub-STS-1
payloads (VT mapped: 28 DS1, 28 J1, or 21 E1 sig-
nals).
Supports standard SPE mappings for STS-1 pay-
loads ( DS3).
Detects STS-1 loss-of-signal (LOS) conditions.
Detects STS-1 out-of-frame and loss-of-frame (OOF/
LOF) conditions.
Provides an 8-bit parallel bus interface for an STS-1
signal.
Provides STS-1 selectable scrambler/descrambler
functions and B1/B2/B3 generation/detection.
Provides STS-1 pointer interpretation. Detects AIS-P
and LOP
.
Provides STS-1 pointer processing.
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.826, G.821, and ETSI 417-1-1.
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STS1 XC Features
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Configurable connection for up to 6 STS1 signals
from 6 SPE mapper transmit blocks to any 1 up to
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Agere Systems Inc.
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