8XC196MD
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability infor-
mation is available in the
Intel
®
Quality System
Handbook.
Table 2. 8XC196MD Memory Map
Description
External Memory or I/O
Internal ROM/EPROM or External
Memory (Determined by EA)
Reserved. Must contain FFH.
(Note 5)
PTS Vectors
Upper Interrupt Vectors
ROM/EPROM Security Key
272323 – 2
Address
0FFFFH
06000H
5FFFH
2080H
207FH
205EH
205DH
2040H
203FH
2030H
202FH
2020H
201FH
201CH
201BH
201AH
2019H
2018H
2017H
2014H
2013H
2000H
1FFFH
1F00H
1EFFH
0200H
01FFH
0018H
0017H
0000H
x
x
Reserved. Must contain FFH.
(Note 5)
Reserved. Must Contain 20H
(Note 5)
NOTE:
EPROMs are available as One Time Programmable
(OTPROM) only.
CCB1
Reserved. Must Contain 20H
(Note 5)
CCB0
Reserved. Must contain FFH.
(Note 5)
Lower Interrupt Vectors
SFR’s
External Memory
488 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1. 3)
Figure 2. The 8XC196MD Family Nomenclature
Table 1. Thermal Characteristics
Package
Type
PLCC
QFP
θ
ja
35
°
C/W
56
°
C/W
θ
jc
13
°
C/W
12
°
C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196MC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196MD
8XC196MC AND 8XC196MD
DIFFERENCES
INT MASK1 INT
PEND1 Registers
PI MASK and PI
PEND Registers
There are some differences between the
8XC196MC
and
8XC196MD
INT MASK1
INT PEND1 registers The 8XC196MD interrupt
mask and pending registers are shown below No-
tice that the CAPCOM5 COMP4 and CAPCOM4
bits are reserved bits on the 8XC196MC The PI bit
of the INT PEND1 register will be set when a
Waveform Generator or Compare Module 5 event
occurs and the corresponding bit in the PI MASK
register is set The PI interrupt vector can be taken
when the PI bit in the INT MASK1 register is set
The 8XC196MC User’s Manual should be refer-
enced for details about the interrupts
INT MASK1 (0031H)
and INT PEND1 (0012H)
7
6
5
PI
4
3
2
1
0
RSV EXTINT
CAPCOM5 COMP4 CAPCOM4 COMP3 CAPCOM3
The PI MASK PI PEND registers contain the bits
for the Compare Module 5 (COMP5) Waveform Gen-
erator (WG) Timer 1 Overflow (TFI) and Timer 2
Overflow (TF2) mask status flag The diagram be-
low shows the registers Notice that the COMP5 bit
is a reserved bit on the 8XC196MC The 8XC196MC
User’s Manual should be referenced for details
about the Waveform Generator Compare Modules
and Timers
PI MASK (1FBEH) and
PEND (1FBCH Read Only)
5
RSV
4
WG
3
RSV
2
TF2
1
RSV
0
TF1
PI
7
RSV
6
COMP5
RSV
e
RESERVED BIT MUST WRITE AS 0
READ AS 1
e
THIS BIT RESERVED ON 8XC196MC
Figure 5 Peripheral Interrupt Mask
and Status Registers
The PI bit in the INT PEND1 register is set if a
Waveform Generator event or Compare Module 5
event occurs and the corresponding PI MASK bit is
set For either of these events to cause an interrupt
the PI bit in the INT MASK1 register and the corre-
sponding event bit in the PI MASK register must be
set
Similarly the TOVF bit in the INT PEND register is
set if Timer 1 or Timer 2 overflow and the corre-
sponding bit in the PI MASK register is set For ei-
ther of these two events to cause an interrupt the
TOVF bit in the INT MASK register and the corre-
sponding event bit in the PI MASK must be set
Upon a PI and or a TOVF interrupt it may be neces-
sary to check if the Compare Module 5 the Wave-
form Generator Timer 1 or Timer 2 event caused
the interrupt The PI PEND will give this informa-
tion However it should be noted that reading the
PI PEND register will clear the register So the indi-
vidual bits in the PI PEND register must be read by
loading PI PEND into another ‘‘shadow’’ register
then checking the ‘‘shadow’’ register to see what
event occurred
RSV
e
RESERVED BIT MUST WRITE AS 0
e
THIS BIT RESERVED ON 8XC196MC
Figure 3 Interrupt Mask and Status Registers
PTSSRV and PTSSEL Register
Similarly there are differences between 8XC196MC
and 8XC196MD PTS registers The 8XC196MD PTS
registers are shown below Notice the CAPCOM5
COMP4 and CAPCOM4 bits are reserved bits on
the 8XC196MC The PI bit in the PTSSRV will be set
when a Waveform Generator or Compare Module 5
end of PTS interrupt occurs and the corresponding
bit in the PI MASK register is set The PI PTS vec-
tor can be used when the PI bit in the PTSSEL regis-
ter is set The 8XC196MC User’s Manual should be
referenced for details about the PTS
PTSSEL (0004H) and PTSSRV (0006H)
15
RSV
14
EXTINT
13
PI
12
CAPCOM5
11
COMP4
10
CAPCOM4
9
8
COMP3 CAPCOM3
7
6
5
4
3
2
1
0
COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 AD DONE TOVF
RSV
e
RESERVED BIT MUST WRITE AS 0
e
THIS BIT RESERVED ON 8XC196MC
Figure 4 PTS Select and Service Registers
4
8XC196MD
Table 3 Interrupt Sources Vectors and Priorities
Interrupt Service
Interrupt Source
Capture Compare5
Compare4
Capture Compare4
Symbol
CAPCOMP5
COMP4
CAPCOMP4
Name
INT12
INT11
INT10
Vector
2038H
2036H
2034H
Priority
12
11
10
Name
PTS12
PTS11
PTS10
PTS Service
Vector
2058H
2056H
2054H
Priority
27
26
25
Interrupt and PTS Vectors
The 8XC196MD has three new interrupt and PTS
vectors which are Capture Compare5 Compare 4
and Capture Compare4 Table 3 shows these inter-
rupt vectors and priorities These are shown as re-
served vectors in the 8XC196MC User’s Manual
Port 7
Port 7 is an additional bidirectional port that was not
available on the 8XC196MC device Port 7 can be
used as I O or some of the pins have special func-
tions The pins are listed below followed by their
special functions
Table 4 Port 7 Special Function Pins
Frequency Generator
The Frequency Generator (FG) Peripheral which
was not available on the 8XC196MC device is avail-
able on the 8XC196MD device The FG outputs a
programmable-frequency 50% duty cycle waveform
on the FREQOUT pin (P7 7) There are two 8-bit reg-
isters which control the FG peripheral
Frequency Generator Control Register
(FG CON) at 1FB8h
Frequency Generator Period Count Register
(FG COUNT) at 1FBAh
The FG CON can be read or written This register
is loaded with a value which determines the number
of counts necessary for toggling the output The fol-
lowing equation should be used to calculate the
FG CON value
FG CON value
e
F
XTAL
b
1
16 (FG Frequency)
Pin
P7 0
P7 1
P7 2
P7 3
P7 4
P7 5
P7 6
P7 7
Special Function
CAPCOMP4
CAPCOMP5
CAPCOMP4
CAPCOMP5
FREQOUT
The special functions of the pins are selected in the
Port 7 SFRs The Port 2 I O Port section of the
8XC196MC User’s Manual can be referenced when
setting up the Port 7 SFRs Port 7 SFRs are located
in the following locations
Table 5 Port 7 Special Function Registers
where FG Frequency is from 4 kHz to 1 MHz
The FG COUNT is loaded with the FG CON reg-
ister value The FG COUNT register is decrement-
ed every eighth state time When it reaches 00h the
FG COUNT register will send a signal to toggle the
output pin and reload the FG COUNT register with
the value in the FG CON register The
FG COUNT can only be read not written
The FREQOUT pin (P7 7) must be configured for a
special function to use it for the Frequency Genera-
tor feature
P7
P7
P7
P7
SFR
MODE
DIR
REG
PIN
Address
1FD1h
1FD3h
1FD5h
1FD7h
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
