JANSR2N7278
Formerly FRL234R4
June 1998
4A, 250V, 0.700 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Intersil Corporation has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Chan-
nel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25m
Ω
. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hard-
ness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to exhibit mini-
mal characteristic changes to total dose (GAMMA) and
neutron (no) exposures. Design and processing efforts are
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
Also available at other radiation and screening levels. See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
[ /Title
(JANS
R2N72
78)
/Sub-
ject
(4A,
250V,
0.700
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
MOS-
FET)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
ductor,
4A,
250V,
0.700
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
Features
• 4A, 250V, r
DS(ON)
= 0.700
Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 4nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Ordering Information
PART NUMBER
JANSR2N7278
PACKAGE
TO-205AF
BRAND
JANSR2N7278
Die family TA17633.
MIL-PRF-19500/604.
Symbol
D
G
S
Packaging
TO-205AF
D
G
S
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev. A
JANSR2N7278
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JANSR2N7278
250
250
4
2
12
±
20
25
10
0.20
12
4
12
-55 to 150
300
1.0
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
Drain to Gate Voltage (R
GS
= 20k
Ω
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
250
-
2.0
1.0
-
-
-
-
-
T
C
= 25
o
C
T
C
= 125
o
C
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 125V,
I
D
= 4A
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
5.0
4.0
-
25
250
100
200
2.94
0.700
1.68
35
85
195
75
120
62
4
12
30
5.0
175
UNITS
V
V
V
V
µ
A
µ
A
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 200V,
V
GS
= 0V
V
GS
=
±
20V
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
Gate to Source Leakage Current
I
GSS
Drain to Source On-State Voltage
Drain to Source On Resistance
V
DS(ON)
r
DS(ON)
V
GS
= 10V, I
D
= 4A
I
D
= 2A,
V
GS
= 10V
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on Slash Sheet)
Gate Charge at 10V
Threshold Gate Charge (Not on Slash Sheet)
Gate Charge Source
Gate Charge Drain
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
R
θ
JC
R
θ
JA
V
DD
= 125V, I
D
= 4A,
R
L
= 31.3
Ω
, V
GS
= 10V,
R
GS
= 25
Ω
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev. A
JANSR2N7278
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
I
SD
= 4A
I
SD
= 4A, dI
SD
/dt = 100A/
µ
s
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 200V
V
GS
= 10V, I
D
= 4A
V
GS
= 10V, I
D
= 2A
MIN
250
2.0
-
-
-
-
MAX
-
4.0
100
25
2.94
0.700
UNITS
V
V
nA
µA
V
Ω
TEST CONDITIONS
MIN
0.6
-
TYP
-
-
MAX
1.8
800
UNITS
V
ns
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts (Note 3)
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 10V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Typical Performance Curves
5
Unless Otherwise Specified
40
T
C
= 25
o
C
I
D
, DRAIN CURRENT (A)
4
I
D
, DRAIN (A)
10
100µs
3
2
1ms
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10ms
100ms
700
1
0
-50
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
NORMALIZED
THERMAL IMPEDANCE (Z
θ
JC
)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
P
DM
t
1
t
2
10
0
10
1
0.01
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev. A
JANSR2N7278
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
50Ω
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
V
DD
t
ON
t
d(ON)
t
OFF
t
d(OFF)
t
r
t
f
90%
R
L
V
DS
V
GS
= 10V
DUT
0V
R
GS
V
DS
90%
10%
10%
90%
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
10V
Q
g
Q
gs
V
G
Q
gd
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev. A
JANSR2N7278
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS)
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
SYMBOL
I
GSS
I
DSS
r
DS(ON)
V
GS(TH)
TEST CONDITIONS
V
GS
=
±20V
V
DS
= 80% Rated Value
T
C
= 25
o
C at Rated I
D
I
D
= 1.0mA
MAX
±20
(Note 4)
±25
(Note 4)
±20%
(Note 5)
±20%
(Note 5)
UNITS
nA
µA
Ω
V
Screening Information
TEST
Gate Stress
Pind
Pre Burn-In Tests (Note 6)
Steady State Gate Bias (Gate Stress)
V
GS
= 30V, t = 250µs
Required
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25
o
C)
MIL-STD-750, Method 1042, Condition B
V
GS
= 80% of Rated Value, T
A
= 150
o
C, Time = 48 hours
All Delta Parameters Listed in the Delta Tests and Limits Table
MIL-STD-750, Method 1042, Condition A
V
DS
= 80% of Rated Value, T
A
= 150
o
C, Time = 240 hours
5%
MIL-S-19500, Group A,
Subgroups 2 and 3
JANS
Interim Electrical Tests (Note 6)
Steady State Reverse Bias (Drain Stress)
PDA
Final Electrical Tests (Note 6)
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
Unclamped Inductive Switching
Thermal Response
Thermal Impedance
SYMBOL
SOA
I
AS
∆V
SD
∆V
SD
TEST CONDITIONS
V
DS
= 200V, t = 10ms
V
GS(PEAK)
= 15V, L = 0.1mH
t
H
= 10ms; V
H
= 25V; I
H
= 2A
t
H
= 500ms; V
H
= 25V; I
H
= 1A
MAX
0.50
12
92
190
UNITS
A
A
mV
mV
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev. A
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