Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT2305A-1 for Standard Drive
IDT2305A-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Power down mode
Available in SOIC package
DESCRIPTION:
The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305A is an 8-pin version of the IDT2309A. IDT2305A accepts
one reference input, and drives out five low skew clocks. The -1H version
of this device operates up to 133MHz frequency and has a higher drive than
the -1 device. All parts have on-chip PLLs which lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305A enters power down.
In this mode, the device will draw less than 12μA for Commercial Tempera-
ture range and less than 25μA for Industrial temperature range
,
the outputs
are tri-stated, and the PLL is not running, resulting in a significant reduction
of power.
The IDT2305A is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
REF
1
PLL
Control
Logic
3
CLK1
2
CLK2
5
CLK3
7
CLK4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2012
Integrated Device Technology, Inc.
AUGUST 2012
DSC 6586/4
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
I
IK
(V
I
< 0)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
A
= 55°C
(in still air)
(3)
T
STG
Operating
Temperature
Operating
Temperature
Input Clamp Current
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Storage Temperature Range
Commercial Temperature
Range
Industrial Temperature
Range
-40 to +85
°C
Max.
–0.5 to +4.6
–0.5 to +5.5
–0.5 to
V
DD
+0.5
–50
±50
±100
0.7
–65 to +150
0 to +70
mA
mA
mA
W
°C
°C
Unit
V
V
V
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
V
DD
CLK3
V
I (2)
V
I
SOIC
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PIN DESCRIPTION
Pin Name
REF
CLK2
(1)
CLK1
GND
CLK3
(1)
V
DD
CLK4
(1)
CLKOUT
(1)
NOTES:
1. Weak pull down on all outputs.
(1)
Pin Number
1
2
3
4
5
6
7
8
Type
IN
Out
Out
Ground
Out
PWR
Out
Out
Output clock
Output clock
Ground
Output clock
3.3V Supply
Output clock
Functional Description
Input reference clock, 5 Volt tolerant input
Output clock, internal feedback on this pin
2
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance < 100MHz
Load Capacitance 100MHz - 133MHz
Input Capacitance
Parameter
Min.
3
0
—
—
—
Max.
3.6
70
30
10
7
pF
Unit
V
°
C
pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD_PD
I
DD
Parameter
Input LOW Voltage Level
Input HIGH Voltage Level
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
Standard Drive
High Drive
Standard Drive
High Drive
REF = 0MHz
Unloaded Outputs at 66.66MHz
I
OL
= 8mA
I
OL
= 12mA (-1H)
I
OH
= -8mA
I
OH
= -12mA (-1H)
—
—
12
32
μA
mA
2.4
—
V
Conditions
Min.
—
2
—
—
—
Max.
0.8
—
50
100
0.4
Unit
V
V
μA
μA
V
SWITCHING CHARACTERISTICS (2305A-1) - COMMERCIAL
Symbol
t
1
Parameter
Output Frequency
Duty Cycle = t
2
÷
t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
10pF Load
30pF Load
Measured at 1.4V, F
OUT
= 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
DD
/2
Conditions
(1,2)
Min.
10
10
40
—
—
—
—
—
—
—
Typ.
—
—
50
—
—
—
0
0
—
—
Max.
133
100
60
2.5
2.5
250
±350
700
170
200
1
Unit
MHz
%
ns
ns
ps
ps
ps
ps
ps
ms
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured at 54-81MHz, loaded outputs
Other frequencies, loaded outputs
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
3
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(1,2)
SWITCHING CHARACTERISTICS (2305A-1H) - COMMERCIAL
Symbol
t
1
Parameter
Output Frequency
Duty Cycle = t
2
÷
t
1
Duty Cycle = t
2
÷
t
1
t
3
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Output Slew Rate
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
10pF Load
30pF Load
Measured at 1.4V, F
OUT
= 66.66MHz
Measured at 1.4V, F
OUT
<50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
DD
/2
Conditions
Min.
10
10
40
45
—
—
—
—
—
1
—
—
Typ.
—
—
50
50
—
—
—
0
0
—
—
—
Max.
133
100
60
55
1.5
1.5
250
±350
700
—
170
200
1
Unit
MHz
%
%
ns
ns
ps
ps
ps
V/ns
ps
ps
ms
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured between 0.8V and 2V using Test Circuit #2
Measured at 54-81MHz, loaded outputs
Other frequencies, loaded outputs
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
OPERATING CONDITIONS - INDUSTRIAL
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance < 100MHz
Load Capacitance 100MHz - 133MHz
Input Capacitance
Parameter
Min.
3
-40
—
—
—
Max.
3.6
+85
30
10
7
pF
Unit
V
°
C
pF
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD_PD
I
DD
Parameter
Input LOW Voltage Level
Input HIGH Voltage Level
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
Standard Drive
High Drive
Standard Drive
High Drive
REF = 0MHz
Unloaded Outputs at 66.66MHz
I
OL
= 8mA
I
OL
= 12mA (-1H)
I
OH
= -8mA
I
OH
= -12mA (-1H)
—
—
25
35
μA
mA
2.4
—
V
Conditions
Min.
—
2
—
—
—
Max.
0.8
—
50
100
0.4
Unit
V
V
μA
μA
V
4
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(1,2)
SWITCHING CHARACTERISTICS (2305A-1) - INDUSTRIAL
Symbol
t
1
Parameter
Output Frequency
Duty Cycle = t
2
÷
t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
10pF Load
30pF Load
Conditions
Min.
10
10
40
—
—
—
—
—
—
—
Typ.
—
—
50
—
—
—
0
0
—
—
Max.
133
100
60
2.5
2.5
250
±350
700
170
200
1
Unit
MHz
%
ns
ns
ps
ps
ps
ps
ps
ms
Measured at 1.4V, F
OUT
= 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured at 54-81MHz, loaded outputs
Other frequencies, loaded outputs
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2305A-1H) - INDUSTRIAL
Symbol
t
1
Parameter
Output Frequency
Duty Cycle = t
2
÷
t
1
Duty Cycle = t
2
÷
t
1
t
3
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Output Slew Rate
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
10pF Load
30pF Load
Conditions
(1,2)
Min.
10
10
40
45
—
—
—
—
—
1
—
—
Typ.
—
—
50
50
—
—
—
0
0
—
—
—
Max.
133
100
60
55
1.5
1.5
250
±350
700
—
170
200
1
Unit
MHz
%
%
ns
ns
ps
ps
ps
V/ns
ps
ps
ms
Measured at 1.4V, F
OUT
= 66.66MHz
Measured at 1.4V, F
OUT
<50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured between 0.8V and 2V using Test Circuit #2
Measured at 54-81MHz, loaded outputs
Other frequencies, loaded outputs
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
ZERO
DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
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