PT6355
VFD Driver/Controller IC
DESCRIPTION
PT6355 is a Vacuum Fluorescent Display Controller
driven 5/16, 6/16, 14/16 and 15/16 duty factors. Eight
to Eighteen Segment Output Lines, Seven to Ten Grid
Output Lines, Ten Segment/Grid Output Drive Lines,
8-bit x 6-channel A-D Converter, Built-in Noise Filter
are all incorporated into a single chip to build a highly
reliable peripheral device for a single chip
micro-computer.
PT6355 also provides 4 serial
interfaces via the CS, SIN, SOUT, SCLK Pins.
Housed in 44-pin, LQFP Package, PT6355’s pin
assignment and application circuit are optimized for
easy PCB layout and cost saving benefits.
FEATURES
•
•
•
•
•
•
CMOS Technology
Internal Pull-Low Resistor
4-Step Dimming Circuitry
8 to 18 Segment Outputs
7 to 10 Grid Outputs
Built-in Noise Filter in Serial Clock and Serial Input
Pins with 2 MHz sampling
•
8-bit x 6 channels Analog-to-Digital Converter with
+3LSB Accuracy
•
Available in 44-pin, LQFP Package
APPLICATION
•
Micro-Computer Peripheral Device
BLOCK DIAGRAM
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6355
PIN DESCRIPTION
Pin Name
VCC
OSC2
VSS
OSC1
/Reset
AN5 to AN0
/CS
SIN
SOUT
SCLK
VEE
I/O
-
O
-
I
I
I
I
I
O
n-channel open drain
I
-
O
p-channel open drain
Description
Power supply
Oscillation output pin
Power supply
Oscillation input pin
Reset input pin
Active ”L”
Internal pull-high resistors are connected between
this pin and the VCC pins.
Analog to digital pin
Chip select
Serial input pin
The clock is read twice with a 2MHz sampling rate
in order to judge if the signal is a noise or not.
Serial output pin
During the Reset condition, this pin is in
high-impedance state.
Serial clock input pin
The clock is read twice with a 2MHz sampling rate
in order to judge if the signal is a noise or not.
Pull-down power supply
Supplies voltage to Pull-down resistors
Grid/Port output pins
This pin acts as either a Grid Output Pin or as an
Ordinary Port Terminal.
During the reset condition, this pin is set to VEE
via a pull-down resistor.
Grid/Segment output pins
This pin acts as either a Grid Output Pin or as an
Segment Output Pin.
During the reset condition, this pin is set to VEE
via a pull-down resistor.
Segment output pin
During the reset condition, this pin is set to VEE
via a pull-down resistor.
Pin No.
1, 44
2
3
4
5
6 to 11
12
13
14
15
16, 17
GR0/P0 to GR7/P7
18 to 25
GR8/SEG17 to GR17/SEG8
O
p-channel open drain
O
p-channel open drain
26 to 35
SEG0 to SEG7
43 to 36
V1.6
4
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