512 Kbit / 1 Mbit / 2 Mbit / 4Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 40MHz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 20MHz)
– Standby Current: 2 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
(2 Mbit and 4 Mbit only)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 125 ms (typical)
– Sector-/Block-Erase Time: 62ms (typical)
– Byte-Program Time: 50 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (5mm x 6mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST25WF512, SST25WF010, SST25WF020, and
SST25WF040 are members of the Serial Flash 25 Series
family and feature a four-wire, SPI-compatible interface that
allows for a low pin-count package which occupies less
board space and ultimately lowers total system costs.
SST25WF512/010/020/040 SPI serial flash memories are
manufactured with SST proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25WF512/010/020/040 devices significantly
improve performance and reliability, while lowering power
consumption. The devices write (Program or Erase) with a
single power supply of 1.65-1.95V for SST25WF512/010/
020/040. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation is less than alternative flash memory technologies.
The SST25WF512/010/020/040 devices are offered in
both 8-lead SOIC and an 8-contact WSON packages. See
Figure 2 for the pin assignment.
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
RST#/HOLD#
1328 F01.0
Note:
In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/busy
status pin. See “End-of-Write Detection” on page 14 for more information.
FIGURE 1: Functional Block Diagram
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
2
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
PIN DESCRIPTION
Top View
CE#
SO
WP#
V
SS
1
2
3
4
8
7
6
5
V
DD
RST#/HOLD#
SCK
SI
1328.25WF 08-soic-P0.0
CE#
SO
WP#
VSS
1
8
VDD
RST#/HOLD#
SCK
SI
2
7
Top View
3
6
4
5
1328 08-wson P2.0
8-Lead SOIC
FIGURE 2: Pin Assignment for 8-Lead SOIC and 8-Contact WSON
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
8-Contact WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 14 for more information.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence which is detailed in “Reset/Hold
Mode” on page 5.
To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020/040
T1.0 1328
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
Chip Enable
Write Protect
Reset
RST#/HOLD#
Hold
V
DD
V
SS
Power Supply
Ground
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
3
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
MEMORY ORGANIZATION
The SST25WF512/010/020/040 SuperFlash memory
arrays are organized in uniform 4 KByte with 16 KByte, 32
KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay eras-
able blocks.
(CE#) is used to select the device, and data is accessed
through the Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK).
The SST25WF512/010/020/040 support both Mode 0
(0,0) and Mode 3 (1,1) of SPI bus operations. The differ-
ence between the two modes, as shown in Figure 3, is the
state of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25WF512/010/020/040 are accessed through
the SPI (Serial Peripheral Interface) bus compatible proto-
col. The SPI bus consist of four control lines; Chip Enable
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1328 F03.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
4
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or
a hold pin. From power-on, the RST#/HOLD# pin defaults
as a hardware reset pin (RST#). The Hold mode for this pin
is a user selected option where an Enable-Hold instruction
enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a
HOLD# pin, and goes back to RST# pin only after a power-
off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin
provides a hardware method for resetting the device. Driving
the RST# pin high puts the device in normal operating
mode. The RST# pin must be driven low for a minimum of
T
RST
time to reset the device. The SO pin is in high imped-
ance state while the device is in reset. A successful reset will
reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active
Program or Erase operation aborts the operation and data
of the targeted address range may be corrupted or lost due
to the aborted erase or program operation. The device exits
AAI Programming Mode in progress and places the SO pin
in high impedance state.
CE#
T
RECR
T
RECP
T
RECE
SCK
T
RST
RST#
T
RHZ
SO
SI
1328 Fx4.0
FIGURE 4: Reset Timing Diagram
TABLE 2: Reset Timing Parameters
Symbol
T
RST
T
RHZ
T
RECR
T
RECP
T
RECE
Parameter
Reset Pulse Width
Reset to High-Z Output
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
Min
100
107
100
10
1
Max
Units
ns
ns
ns
µs
ms
T2.1328
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
5
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