8Mbit 1.8V SPI Serial Flash
SST25WF080
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 75 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 33 MHz)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-bump XFBGA
• All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST25WF080 is a member of the Serial Flash 25
Series family and features a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total sys-
tem costs. SST25WF080 SPI serial flash memory is manu-
factured with SST proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25WF080 significantly improves performance and
reliability, while lowering power consumption. The device
writes (Program or Erase) with a single power supply of
1.65-1.95V for SST25WF080. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
memory technologies.
The SST25WF080 is offered in both an 8-lead, 150 mils
SOIC package and an 8-bump XFBGA package. See Fig-
ures 2 and 3 for the pin assignments.
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
RST#/HOLD#
1203 F01.0
Note:
In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/busy
status pin. See “End-of-Write Detection” on page 12 for more information.
FIGURE 1: Functional Block Diagram
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
2
8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
PIN DESCRIPTION
Top View
CE#
SO
WP#
V
SS
1
2
3
4
8
7
6
5
V
DD
RST#/HOLD#
SCK
SI
1203.25WF 08-soic-P0.0
FIGURE 2: Pin Assignment for 8-Lead SOIC
Top View
(Balls Facing Down)
2
SI
SCK
RST#/
HOLD#
V
DD
CE#
1
V
SS
WP#
SO
A
B
C
D
1328.25WF 8-xfbga P1.0
FIGURE 3: Pin Assignment for 8-bump XFBGA
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 12 for more information.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 5.
To provide power supply voltage: 1.65-1.95V for SST25WF080
T1.0 1203
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
RST#/HOLD#
Chip Enable
Write Protect
Reset
Hold
V
DD
V
SS
Power Supply
Ground
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
3
8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
MEMORY ORGANIZATION
The SST25WF080 SuperFlash memory arrays are orga-
nized in uniform 4 KByte sectors with 16 KByte, 32 KByte,
and 64 KByte overlay erasable blocks.
The SST25WF080 support both Mode 0 (0,0) and Mode 3
(1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 4, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25WF080 are accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1203 F03.0
HIGH IMPEDANCE
FIGURE 4: SPI Protocol
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
4
8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or
a hold pin. From power-on, the RST#/HOLD# pin defaults
as a hardware reset pin (RST#). The Hold mode for this pin
is a user selected option where an Enable-Hold instruction
enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a
HOLD# pin, and goes back to RST# pin only after a power-
off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin
provides a hardware method for resetting the device. Driving
the RST# pin high puts the device in normal operating
mode. The RST# pin must be driven low for a minimum of
T
RST
time to reset the device. The SO pin is in high imped-
ance state while the device is in reset. A successful reset will
reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active
Program or Erase operation aborts the operation and data
of the targeted address range may be corrupted or lost due
to the aborted erase or program operation. The device exits
AAI Programming Mode in progress and places the SO pin
in high impedance state.
CE#
T
RECR
T
RECP
T
RECE
SCK
T
RST
RST#
T
RHZ
SO
SI
1203 F04.0
FIGURE 5: Reset Timing Diagram
TABLE 2: Reset Timing Parameters
Symbol
T
RST
1
Parameter
Reset Pulse Width
Reset to High-Z Output
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
Min
100
Max
107
100
10
1
Units
ns
ns
ns
µs
ms
T2.1203
T
RHZ
T
RECR
T
RECP
T
RECE
1. For reset while in a Programming or Erase mode, the reset pulse must be >5µs
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
5
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