8 Mbit SPI Serial Flash
SST25VF080B
SST25VF080B8Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 50/66 MHz conditional (see Table 13)
- (SST25VF080B-50-xx-xxxx)
– 80 MHz
- (SST25VF080B-80-xx-xxxx)
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (6mm x 5mm)
– 8-lead PDIP (300 mils)
• All devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. The SST25VF080B devices are
enhanced with improved operating frequency and lower
power consumption. SST25VF080B SPI serial flash mem-
ories are manufactured with SST’s proprietary, high-perfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate
approaches.
The SST25VF080B devices significantly improve perfor-
mance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
supply of 2.7-3.6V for SST25VF080B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The SST25VF080B device is offered in 8-lead SOIC (200
mils), 8-contact WSON (6mm x 5mm), and 8-lead PDIP
(300 mils) packages. See Figure 2 for pin assignments.
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
1296 B1.0
CE#
SCK
SI
SO
WP#
HOLD#
FIGURE 1: Functional Block Diagram
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
2
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
1296 08-soic S2A P1.0
3
Top View
6
4
5
1296 08-wson QA P2.0
8-lead SOIC
CE#
VDD
8-contact WSON
SO
Top View
HOLD#
WP#
SCK
VSS
SI
1296 08-pdip-PA-P3.0
8-lead PDIP
FIGURE 2: Pin Assignments
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply voltage: 2.7-3.6V for SST25VF080B
T1.0 1296
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
HOLD#
V
DD
V
SS
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
3
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
MEMORY ORGANIZATION
The SST25VF080B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF080B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF080B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1296 SPIprot.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
4
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
Hold Operation
The HOLD# pin is used to pause a serial sequence under-
way with the SPI flash memory without resetting the clock-
ing sequence. To activate the HOLD# mode, CE# must be
in active low state. The HOLD# mode begins when the
SCK active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
24 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1296 HoldCond.0
FIGURE 4: Hold Condition Waveform
Write Protection
SST25VF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register pro-
vide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 2: Conditions to execute Write-Status-
Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T2.0 1296
©2010 Silicon Storage Technology, Inc.
S71296-04-000
01/10
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
