4 Mbit SPI Serial Flash
SST25VF040
SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
EOL Product Data Sheet
FEATURES:
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 20 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
• Packages Available
– 8-lead SOIC 200 mil body width
– 8-contact WSON (5mm x 6mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST serial flash family features a four-wire, SPI-
compatible interface that allows for a low pin-count pack-
age occupying less board space and ultimately lowering
total system costs. SST25VF040 SPI serial flash memo-
ries are manufactured with SST proprietary, high perfor-
mance CMOS SuperFlash Technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches.
The SST25VF040 device significantly improves perfor-
mance, while lowering power consumption. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash memory technologies. The
SST25VF040 device operates with a single 2.7-3.6V
power supply.
The SST25VF040 device is offered in an 8-lead SOIC 200
mil body width (S2A) package and in an 8-contact WSON
package. See Figure 2 for the pin assignments.
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
09/10
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit SPI Serial Flash
SST25VF040
EOL Product Data Sheet
X - Decoder
Address
Buffers
and
Latches
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
1231 B1.0
CE#
SCK
SI
SO
WP#
HOLD#
FIGURE 1: Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
09/10
2
4 Mbit SPI Serial Flash
SST25VF040
EOL Product Data Sheet
PIN DESCRIPTION
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
1231 08-soic P1.0
Top View
3
6
4
5
1231 08-wson P2.0
8-
LEAD
SOIC
FIGURE 2: Pin Assignments
TABLE 1: Pin Description
Symbol Pin Name
SCK
Serial Clock
Functions
8-
CONTACT
WSON
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
To provide power supply (2.7-3.6V).
T1.0 1231(04)
SI
SO
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data
Input
Serial Data
Output
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
09/10
3
4 Mbit SPI Serial Flash
SST25VF040
EOL Product Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: Product Identification
Address
Manufacturer’s ID
Device ID
SST25VF040
00001H
44H
T2.0 1231(04)
DEVICE OPERATION
The SST25VF040 is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF040 supports both Mode 0 (0,0) and Mode 3
(1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
Data
BFH
00000H
MEMORY ORGANIZATION
The SST25VF040 SuperFlash memory array is organized
in 4 KByte sectors with 32 KByte overlay blocks.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1231 F02.1
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
09/10
4
4 Mbit SPI Serial Flash
SST25VF040
EOL Product Data Sheet
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH
.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
18 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1231 F03.0
FIGURE 4: Hold Condition Waveform
Write Protection
SST25VF040 provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See
Table 5 for Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 3: Conditions to execute Write-Status-
Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 1231(04)
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
09/10
5
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