ECLLQFP32EVB
Evaluation Board User's
Manual for High Frequency
LQFP32
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EVAL BOARD USER’S MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board
for the devices in 32−lead LQFP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 32−lead LQFP device
samples. The board provides a high bandwidth 50
W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
•
•
•
•
Information on 32−lead LQFP Evaluation Board
Assembly Instructions
Appropriate Lab Setup
Bill of Materials
The 32−lead LQFP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay−Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50
W
internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground. The FR4 dielectric
material is placed between second and third layer and
between third and fourth layer. The third layer is the power
plane (V
CC
and V
EE
) and a portion of this layer is a ground
plane. The fourth layer is the secondary trace layer.
Figure 1. Top View of the 32−lead LQFP Evaluation Board
©
Semiconductor Components Industries, LLC, 2012
January, 2012
−
Rev. 3
1
Publication Order Number:
EVBUM2055/D
ECLLQFP32EVB
Bottom View
Enlarged Bottom View
Figure 2. Bottom View of the 32−lead LQFP Evaluation Board
LAY−UP DETAIL
4 LAYER
SILKSCREEN (TOP SIDE)
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR−4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR−4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
0.062
$
0.007
Figure 3. Evaluation Board Lay−up
Board Layout
The 32−lead LQFP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least thirteen possible configurable options. Table 1, list
the devices and the relevant configuration that utilizes this
PCB board. Lists of components and simple schematics are
located in Figures 6 through 18. Place SMA connectors on
J1 through J32, 50
W
chip resistors between ground pad and
Pin 1 pad through Pin 32 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
mF
and C1, C2, and C3 are 0.1
mF);
(See Figure 5).
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ECLLQFP32EVB
Evaluation Board Assembly Instructions
The 32−lead LQFP evaluation board is designed for
characterizing devices in a 50
W
laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of placing a termination
resistor depending on the input/output configuration (see
Table 1, Configuration List). Table 17 contains the Bill of
Materials for this evaluation board.
Solder the Device on the Evaluation Board
It is recommended to solder 0.01
mF
capacitors to C4 and
C5 to reduce the unwanted noise from the power supplies.
C1, C2, and C3 pads are provided for 0.1
mF
capacitor to
further diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Termination
The soldering can be accomplished by hand soldering or
soldering re−flow techniques. Make sure pin 1 of the device
is located next to the white dotted mark and all the pins are
aligned to the footprint pads. Solder the 32−lead LQFP
device to the evaluation board.
Connecting Power and Ground Planes
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50
W
internal impedance in
the oscilloscope to be used as a termination of the ECL
signals (V
TT
= V
CC
– 2.0 V, in split power supply setup, V
TT
is the system ground, V
CC
is 2.0 V, and V
EE
is –3.0 V or
–1.3 V; see Table 2, Power Supply Levels).
Table 2. Power Supply Levels
Power Supply
5.0 V
3.3 V
2.5 V
V
CC
2.0 V
2.0 V
2.0 V
V
EE
−3.0
V
−1.3
V
−0.5
V
GND
0.0 V
0.0 V
0.0 V
All ECL outputs need to be terminated to V
TT
(V
TT
= V
CC
–2.0 V = GND) via a 50
W
resistor. 0402 chip resistor pads
are provided on the bottom side of the evaluation board to
terminate the ECL driver (More information on termination
is provided in AN8020). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads. For ease of assembly,
it is advised to place and solder termination resistors on its
vertical (side) position, instead of its original or flat position.
Installing the SMA Connectors
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board on J1
through J32. Please note that alignment of the signal
connector pin of the SMA can influence the lab results. The
reflection and launch of the signals are largely influenced by
imperfect alignment and soldering of the SMA connector.
Validating the Assembled Board
Connect three banana jack sockets to V
CC
, V
EE
, and GND
labeled holes. Wire bond the appropriate device pin pad on
the bottom side of the board to V
CC
and V
EE
power stripes.
(Device specific, please see configuration for each desired
device. See Figure 5)
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.
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