CY8C23433, CY8C23533
PSoC
®
Programmable System-on-Chip™
Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
3.0 to 5.25V Operating Voltage
❐
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
❐
4 Rail-to-Rail analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐
4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
❐
Complex Peripherals by Combining Blocks
❐
High-Speed 8-Bit SAR ADC Optimized for Motor Control
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
❐
8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Programmable Pin Configurations
❐
25 mA Sink on all GPIO
❐
Pull up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to Ten Analog Inputs on GPIO
❐
Two 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on All GPIO
Additional System Resources
2
❐
I C™ Slave, Master, and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full-Featured In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
■
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Global Analog Interconnect
Flash 8K
Sleep and
Watchdog
SROM
CPUCore (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
1 Row
4 Blocks
ANALOG SYSTEM
Analog
Block Array
2 Columns
4 Blocks
Analog
Ref
■
SAR8 ADC
Analog
Input
Muxing
■
Digital
Clocks
Multiply
Accum.
Decimator
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
■
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 05, 2008
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CY8C23433, CY8C23533
PSoC Functional Overview
The PSoC family consists of many mixed-signal array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
a low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
The PSoC architecture, as shown in the
Logic Block Diagram
on
page 1, consists of four main areas: PSoC Core, Digital System,
Analog System, and System Resources. Configurable global
busing allows combining all the device resources into a complete
custom system. The PSoC CY8C23x33 family can have up to
three IO ports that connect to the global digital and analog
interconnects, providing access to four digital blocks and four
analog blocks.
Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks
FromCore
To System Bus
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity (up to 1)
SPI master and slave (up to 1)
I2C slave and master (1 available as a System Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to 1)
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled
PSoC Device Character-
istics
on page 4.
Document Number: 001-44369 Rev. *B
Page 2 of 37
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Analog System
The Analog system consists of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block consists of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
Filters (2 band pass, low-pass)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (1, with 16 selectable thresholds)
Array Input Configuration
DAC (6 or 9 -bit DAC)
Multiplying DAC (6 or 9 -bit DAC)
High current output drivers (two with 30 mA drive)
1.3V reference (as a System Resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P0[7:0]
ACI2[3:0]
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-44369 Rev. *B
Page 3 of 37
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Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
low voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow:
■
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Mixed-Signal
Array Technical Reference Manual.
For latest Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
at
http://www.cypress.com/psoc.
To determine which PSoC device meets your requirements,
navigate through the PSoC Decision Tree in the Application Note
AN2209
at
http://www.cypress.com
and select Application Notes
under the Design Resources.
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
■
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/onlinestore.
■
■
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
analog
and
CapSense.
Go
to
http://www.cypress.com.
■
PSoC Device Characteristics
Depending on the PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
Table 1. PSoC Device Characteristics
Analog
Columns
Analog
Blocks
Analog
Outputs
Analog
Inputs
Digital
Blocks
Digital
IO
Digital
Rows
PSoC Part
Number
CY8C29x66
CY8C27x43
CY8C24x94
CY8C23X33
SAR8
ADC
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
http://www.cypress.com,
click on Design
Support located at the top of the web page, and select CYPros
Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at
http://www.cypress.com/support.
up to 4
64
up to 2
44
56
1
up to 1
26
16
8
4
4
4
4
4
0
12
12
48
12
12
28
8
28
4
4
2
2
2
0
0
0
4
4
2
2
[1]
2
2
2
0
12
12
6
4
6
4
[2]
4
[2]
3
[3]
No
No
No
Yes
No
No
No
No
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com/psocapnotes.
CY8C24x23A up to 1
24
CY8C21x34
CY8C21x23
CY8C20x34
up to 1
28
16
1
up to 0
28
Notes
1. One complete column, plus one Continuous Time Block.
2. Limited analog functionality
.
3. Two analog blocks and one CapSense.
Document Number: 001-44369 Rev. *B
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Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP (refer section
PSoC Designer
Subsystems
on page 5).
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. Once the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
Results
PSoC
Designer
Graphical Designer
Interface
Context
Sensitive
Help
Commands
Importable
Design
Database
Device
Database
Application
Database
Project
Database
User
Modules
Library
PSoC
Configuration
Sheet
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
PSoC
Designer
Core
Engine
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler.
The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode, and linked with other software modules to get
absolute addressing.
C Language Compiler.
A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Manufacturing
Information
File
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Document Number: 001-44369 Rev. *B
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