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Freescale Semiconductor

Technical Data

Document Number: MPC8544EEC

Rev. 4, 09/2010

MPC8544E PowerQUICC III

Integrated Processor

Hardware Specifications

1

MPC8544E Overview

Contents

MPC8544E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .16

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Enhanced Three-Speed Ethernet (eTSEC),

MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Programmable Interrupt Controller . . . . . . . . . . . . . .55

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . .63

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .81

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

System Design Information . . . . . . . . . . . . . . . . . . .105

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . .114

Document Revision History . . . . . . . . . . . . . . . . . . .116

This section provides a high-level overview of MPC8544E

features.

Figure 1

shows the major functional units within

the device.

1.1

Key Features

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The following list provides an overview of the device feature

set:

• High-performance, 32-bit core enhanced by

resources for embedded cores defined by the Power

ISA, and built on Power Architecture® technology:

— 32-Kbyte L1 instruction cache and 32-Kbyte L1

data cache with parity protection. Caches can be

locked entirely or on a per-line basis, with

separate locking for instructions and data.

— Signal-processing engine (SPE) APU (auxiliary

processing unit). Provides an extensive

instruction set for vector (64-bit) integer and

fractional operations. These instructions use both

the upper and lower words of the 64-bit GPRs as

they are defined by the SPE APU.

MPC8544E Overview

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

— Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

— Performance monitor facility that is similar to, but separate from, the device performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

• 256-Kbyte L2 cache/SRAM

— Flexible configuration

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI and PCI Express

– Four outbound windows plus default translation for PCI and PCI Express

• DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

2

Freescale Semiconductor

MPC8544E Overview

•

Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports

Full ECC support

Page mode support

– Up to 16 simultaneous open pages for DDR

– Up to 32 simultaneous open pages for DDR2

— Contiguous or discontiguous memory mapping

— Sleep mode support for self-refresh SDRAM

— On-die termination support when using DDR2

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access via JTAG port

— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports a variety of other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing.

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.

— Interrupt summary registers allow fast identification of interrupt source.

Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,

IKE, WTLS/WAP, SSL/TLS, and 3GPP

— Four crypto-channels, each supporting multi-command descriptor chains

– Dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— PKEU—public key execution unit

– RSA and Diffie-Hellman; programmable field size up to 2048 bits

– Elliptic curve cryptography with F

2

m and F(p) modes and programmable field size up to

511 bits

— DEU—Data Encryption Standard execution unit

– DES, 3DES

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

—

Freescale Semiconductor

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MPC8544E Overview

•

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— AESU—Advanced Encryption Standard unit

– Implements the Rijndael symmetric key cipher

– ECB, CBC, CTR, and CCM modes

– 128-, 192-, and 256-bit key lengths

— AFEU—ARC four execution unit

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— MDEU—message digest execution unit

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— KEU—Kasumi execution unit

– Implements F8 algorithm for encryption and F9 algorithm for integrity checking

– Also supports A5/3 and GEA-3 algorithms

— RNG—random number generator

— XOR engine for parity checking in RAID storage applications

Dual I

2

C controllers

— Two-wire interface

— Multiple master support

— Master or slave I

2

C mode support

— On-chip digital filtering rejects spikes on the bus

Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I

2

C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I

2

C addressing mode

— Data integrity checked with preamble signature and CRC

DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

Local bus controller (LBC)

— Multiplexed 32-bit address and data bus operating at up to 133 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.

— Two protocol engines available on a per chip select basis:

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

4

Freescale Semiconductor

MPC8544E Overview

•

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

— Parity support

— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

Two enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Two IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, and

IEEE 802.3ab-compliant controllers

— Support for various Ethernet physical interfaces:

– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, SGMII, and RGMII.

– 10/100 Mbps full- and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII.

— Flexible configuration for multiple PHY interface configurations.

— TCP/IP acceleration and QoS features available

– IP v4 and IP v6 header recognition on receive

– IP v4 header checksum verification and generation

– TCP and UDP checksum verification and generation

– Per-packet configurable acceleration

– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS

stacks, and ESP/AH IP-security headers

– Supported in all FIFO modes

— Quality of service support:

– Transmission from up to eight physical queues

– Reception to up to eight physical queues

— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):

– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame generation and recognition)

— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE Std 802.1™ virtual local area network (VLAN) tags and priority

— VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

— Retransmission following a collision

— CRC generation and verification of inbound/outbound frames

— Programmable Ethernet preamble insertion and extraction of up to 7 bytes

— MAC address recognition:

– Exact match on primary and virtual 48-bit unicast addresses

– VRRP and HSRP support for seamless router fail-over

– Up to 16 exact-match MAC addresses supported

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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MPC8544E_10

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