DP
AK
BUJ302AD
NPN power transistor
Rev. 01 — 28 March 2011
Product data sheet
1. Product profile
1.1 General description
High-voltage, high-speed planar-passivated NPN power switching transistor in a SOT428
(DPAK) surface mounted package.
1.2 Features and benefits
Fast switching
High voltage capability
Low thermal resistance
Surface-mountable package
1.3 Applications
DC-to-DC converters
High-frequency electronic lighting
ballast applications
Inverters
Motor control systems
1.4 Quick reference data
Table 1.
Symbol
I
C
P
tot
V
CESM
Quick reference data
Parameter
collector current
total power dissipation
collector-emitter peak
voltage
DC current gain
Conditions
see
Figure 1;
see
Figure 2;
see
Figure 4
T
mb
≤
25 °C; see
Figure 3
V
BE
= 0 V
Min
-
-
-
Typ
-
-
-
Max Unit
4
80
A
W
1050 V
Static characteristics
h
FE
I
C
= 0.1 A; V
CE
= 5 V;
T
mb
= 25 °C; see
Figure 11
I
C
= 0.8 A; V
CE
= 3 V;
T
mb
= 25 °C; see
Figure 12
[1]
Pulse test: pulse duration
≤
300 µs, duty cycle
≤
2 %
[1]
48
25
66
42
100
50
[1]
NXP Semiconductors
BUJ302AD
NPN power transistor
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
B
C
E
C
base
collector
[1]
emitter
mounting base; connected to
collector
2
1
3
mb
B
E
sym123
Simplified outline
Graphic symbol
C
SOT428 (DPAK)
[1]
it is not possible to make a connection to pin 2 of the SOT428 (DPAK) package
3. Ordering information
Table 3.
Ordering information
Package
Name
BUJ302AD
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
4. Limiting values
Table 4.
Symbol
V
CESM
V
CEO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
V
EBO
Limiting values
Parameter
collector-emitter peak voltage
collector-emitter voltage
collector current
peak collector current
base current
peak base current
total power dissipation
storage temperature
junction temperature
emitter-base voltage
I
C
= 0 A; I
E
= 2 A; t
p
< 10 ms
T
mb
≤
25 °C; see
Figure 3
Conditions
V
BE
= 0 V
I
B
= 0 A
see
Figure 1;
see
Figure 2;
see
Figure 4
Min
-
-
-
-
-
-
-
-65
-
-
Max
1050
400
4
8
2
4
80
150
150
24
Unit
V
V
A
A
A
A
W
°C
°C
V
In accordance with the Absolute Maximum Rating System (IEC 60134).
BUJ302AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 01 — 28 March 2011
2 of 14
NXP Semiconductors
BUJ302AD
NPN power transistor
10
I
C
(A)
8
003aag027
V
CC
L
C
V
CL(CE)
probe point
6
I
Bon
V
BB
L
B
DUT
001aab999
4
2
0
0
400
800
1200
V
CEclamp
(V)
Fig 1.
Reverse bias safe operating area
120
P
der
(%)
80
Fig 2.
Test circuit for reverse bias safe operating area
001aab993
40
0
0
40
80
120
T
mb
(°C)
160
Fig 3.
Normalized total power dissipation as a function of mounting base temperature
BUJ302AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 01 — 28 March 2011
3 of 14
NXP Semiconductors
BUJ302AD
NPN power transistor
10
2
I
C
(A)
10
I
CM(max)
I
C(max)
(1)
001aac001
duty cycle = 0.01
II
(3)
t
p
= 20
μs
50
μs
100
μs
200
μs
500
μs
DC
1
(2)
10
−1
10
−2
I
(3)
III
(3)
10
−3
1
10
10
2
V
CEclamp
(V)
10
3
1)Ptot maximum and Ptot peak maximum lines
2)Second breakdown limits
3) I = Region of permissable DC operation
II = Extension for repetitive pulse operation
III = Extension during turn-on in single transistor converters
provided that RBE
≤
100
Ω
and tp
≤
0.6
μs
Fig 4.
Forward bias safe operating area for Tmb
≤
25 °C
BUJ302AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 01 — 28 March 2011
4 of 14
NXP Semiconductors
BUJ302AD
NPN power transistor
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to
mounting base
Conditions
see
Figure 5
Min
-
-
Typ
-
60
Max
1.56
-
Unit
K/W
K/W
thermal resistance from junction to ambient in free air
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
−1
0.05
0.02
0.01
t
p
T
P
tot
001aab998
δ
=
t
p
T
t
10
−2
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse width
BUJ302AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 01 — 28 March 2011
5 of 14
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
