DISCRETE SEMICONDUCTORS
DATA SHEET
BUJ105AB
Silicon Diffused Power Transistor
Product
specification
October 2001
NXP
Semiconductors
Product specification
Silicon Diffused Power Transistor
BUJ105AB
GENERAL DESCRIPTION
High-voltage, high-speed planar-passivated npn power switching transistor in SOT404 (D
2
-PAK) surface-mount
package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching
regulators, motor control systems, etc.
QUICK REFERENCE DATA
SYMBOL
V
CESM
V
CBO
V
CEO
I
C
I
CM
P
tot
V
CEsat
h
FEsat
t
f
PARAMETER
Collector-emitter voltage peak value
Collector-Base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Fall time
CONDITIONS
V
BE
= 0 V
TYP.
-
-
-
-
-
-
0.3
11
20
MAX.
700
700
400
8
16
125
1.0
15
50
UNIT
V
V
V
A
A
W
V
ns
T
mb
≤
25 ˚C
I
C
= 4.0 A;I
B
= 0.8 A
I
C
= 4.0 A; V
CE
= 5 V
I
C
= 5 A; I
B1
= 1 A
PINNING - SOT404
PIN
1
2
3
mb
base
collector
emitter
collector
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
c
b
2
1
3
e
LIMITING VALUES8
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CESM
V
CEO
V
CBO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
PARAMETER
Collector to emitter voltage
Collector to emitter voltage (open base)
Collector to base voltage (open emitter)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
V
BE
= 0 V
MIN.
-
-
-
-
-
-
-
-
-65
-
MAX.
700
400
700
8
16
4
8
125
150
150
UNIT
V
V
V
A
A
A
A
W
˚C
˚C
T
mb
≤
25 ˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to mounting
base
Thermal resistance junction to ambient
minimum footprint, FR4 board
CONDITIONS
TYP.
-
55
MAX.
1.0
-
UNIT
K/W
K/W
October 2001
1
Rev 1.000
NXP
Semiconductors
Product specification
Silicon Diffused Power Transistor
BUJ105AB
STATIC CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
I
CES
,I
CBO
I
CES
I
CEO
I
EBO
V
CEOsust
V
CEsat
V
BEsat
h
FE
h
FE
h
FEsat
PARAMETER
Collector cut-off current
1
CONDITIONS
V
BE
= 0 V; V
CE
= V
CESMmax
V
BE
= 0 V; V
CE
= V
CESMmax
;
T
j
= 125 ˚C
V
CEO
= V
CEOMmax
(400V)
V
EB
= 9 V; I
C
= 0 A
I
B
= 0 A; I
C
= 10 mA;
L = 25 mH
I
C
= 4.0 A;I
B
= 0.8 A
I
C
= 4.0 A;I
B
= 0.8 A
I
C
= 1 mA; V
CE
= 5 V
I
C
= 500 mA; V
CE
= 5 V
I
C
= 4.0 A; V
CE
= 5 V
MIN.
-
-
-
-
400
-
-
10
13
8
TYP.
-
-
-
-
-
0.3
1.0
14
23
11
MAX.
0.2
0.5
0.1
1
-
1.0
1.5
34
36
15
UNIT
mA
mA
mA
mA
V
V
V
Collector cut-off current
Emitter cut-off current
Collector-emitter sustaining voltage
Collector-emitter saturation voltage
Base-emitter saturation voltage
DC current gain
DYNAMIC CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
Switching times (resistive load)
t
on
t
s
t
f
t
s
t
f
t
s
t
f
Turn-on time
Turn-off storage time
Turn-off fall time
Switching times (inductive load)
Turn-off storage time
Turn-off fall time
Switching times (inductive load)
Turn-off storage time
Turn-off fall time
CONDITIONS
I
Con
= 5 A; I
Bon
= -I
Boff
= 1 A;
R
L
= 75 ohms; V
BB2
= 4 V;
TYP.
MAX.
UNIT
0.65
1.8
0.3
1
2.5
0.5
µs
µs
µs
I
Con
= 5 A; I
Bon
= 1 A; L
B
= 1
µH;
-V
BB
= 5 V
I
Con
= 5 A; I
Bon
= 1 A; L
B
= 1
µH;
-V
BB
= 5 V; T
j
= 100 ˚C
1.2
20
1.7
50
µs
ns
1.4
25
1.9
100
µs
ns
1
Measured with half sine-wave voltage (curve tracer).
October 2001
2
Rev 1.000
NXP
Semiconductors
Product specification
Silicon Diffused Power Transistor
BUJ105AB
+ 50v
100-200R
IC
90 %
ICon
90 %
10 %
Horizontal
Oscilloscope
Vertical
300R
30-60 Hz
6V
1R
IB
ts
ton
toff
IBon
10 %
tr
30ns
-IBoff
tf
Fig.1. Test circuit for V
CEOsust
.
Fig.4. Switching times waveforms with resistive load.
IC / mA
VCC
250
LC
IBon
100
10
0
VCE / V
LB
T.U.T.
-VBB
min
VCEOsust
Fig.2. Oscilloscope display for V
CEOsust
.
Fig.5. Test circuit inductive load.
= 300 V; -V
BE
= 5 V; L
C
= 200 uH; L
B
= 1 uH
VCC
VCC
ICon
90 %
IC
RL
VIM
0
tp
IB
RB
T.U.T.
ts
toff
IBon
10 %
tf
t
T
-IBoff
t
Fig.3. Test circuit resistive load. V
IM
= -6 to +8 V
V
CC
= 250 V; t
p
= 20
µs; δ
= t
p
/ T = 0.01.
R
B
and R
L
calculated from I
Con
and I
Bon
requirements.
Fig.6. Switching times waveforms with inductive load.
October 2001
3
Rev 1.000
NXP
Semiconductors
Product specification
Silicon Diffused Power Transistor
BUJ105AB
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
VCEsat/V
2.0
1.6
IC=1A
1.2
2A
3A
4A
0.8
0.4
0
20
40
60
80
Tmb / C
100
120
140
0.0
0.01
0.10
IB/A
1.00
10.00
Fig.7. Normalised power dissipation.
PD% = 100⋅PD/PD
25˚C
= f (T
mb
)
Fig.10. Collector-Emitter saturation voltage.
Solid lines = typ values, V
CEsat
= f(IB); T
j
=25˚C.
HFE
50
VBESAT/V
1.4
30
Tj=100C
1.3
20
25C
1.2
15
1.1
-40C
10
1
0.9
5
-40C
0.8
25C
Tj=100C
0.7
2
VCE=1V
0.6
0.01
0.05
0.1
0.3
IC/A
1
2
3
5
10
0.5
0.1
0.5
1
IC/A
2
5
10
Fig.8. Typical DC current gain. h
FE
= f(I
C
)
parameter V
CE
Fig.11. Base-Emitter saturation voltage.
Solid lines = typ values, V
BEsat
= f(IC); at IC/IB =4.
HFE
50
VCESAT/V
0.6
30
Tj=100C
0.5
Tj=100C
20
25C
0.4
15
-40C
10
0.3
0.2
25C
5
-40C
VCE=5V
0.1
2
0.01
0.05
0.1
0.3
IC/A
1
2
3
5
10
0
0.2
0.4
0.6
1
IC/A
2
5
6
Fig.9. Typical DC current gain. h
FE
= f(I
C
)
parameter V
CE
Fig.12. Collector-Emitter saturation voltage.
Solid lines = typ values, V
CEsat
= f(IC); at IC/IB =4.
October 2001
4
Rev 1.000
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