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MN101CA3

产品描述MN101CA3 Series
文件大小324KB,共3页
制造商Panasonic(松下)
官网地址http://www.panasonic.co.jp/semicon/e-index.html
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MN101CA3概述

MN101CA3 Series

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MN101CA3 Series
Type
Internal ROM type
ROM (byte)
RAM (byte)
Package (Lead-free)
Minimum Instruction
Execution Time
MN101CA3F
Mask ROM
96K
4K
MN101CFA3G
FLASH
128K
10K
QFP100-P-1818B
0.1
µs (at
4.5
V to
5.5
V,
20
MHz)
0.24
µs (at
2.7
V to
5.5
V,
8.4
MHz)
0.48
µs (at
2.3
V to
5.5
V,
4.19
MHz)*
1.0
µs (at
2.0
V to
5.5
V,
2.0
MHz)*
62.5
µs (at
2.0
V to
5.5
V,
32
kHz)*
*: The lower limit for operation guarantee for flash memory built-in type is
2.5
V.
Interrupts
RESET. Watchdog. External
0
to
6.
Timer
0
to
4.
Timer
6.
Timer
7
(2 systems). Timer
8
(2 systems). Time base. Serial
0
(2 systems).
Serial
1
(2 systems). Serial
2.
Serial
3
(2 systems). A/D conversion finish. Automatic transfer finish. FL display key scan. FL display
dimmer
Timer Counter
8-bit
timer
×
6
Timer
0
..................Square-wave/8-bit PWM output. Event count. Remote control carrier output. Simple pulse width measurement
Timer
1
..................Square-wave output. Event count. Serial transfer clock output
Timer
2, 4
..............Square-wave/8-bit PWM output. Serial transfer clock output. Event count. Simple pulse width measurement
Timer
3
..................Square-wave output. Event count. Remote control carrier output. Serial transfer clock output
Timer
6
..................8-bit freerun timer
Timer
0, 1
can be cascade-connected
Timer
2, 3
can be cascade-connected
16-bit
timer
×
2
Timer
7, 8
..............Square-wave output.
16-bit
PWM output (cycle/duty continuous variable). Event count. Pulse width measurement.
Input capture
Time base timer: One-minute count setting
Watchdog timer
×
1
Serial interface
Synchronous type/UART (full-duplex)
×
2:
Serial
0, 1
Synchronous type/Single-master I
2
C
×
1:
Serial
2
UART (full-duplex)
×
1:
Serial
3
DMA controller
Maximum transfer cycles:
255
Starting factor: External request. Various types of interrupt. Software
Transfer mode:
1-byte
transfer. Word transfer. Burst transfer
I/O Pins
I/O
High Voltage
36
:
Common use. Specified pull-up resistor available. Input/output selectable (bit unit)
53
:
Output:
26.
I/O:
27.
P-ch. open drain (breakdown voltage –40 V): FL drive:
53.
Specified pull-down resistor mask
option:
35
A/D converter
8-bit
×
8
channels (with S/H)
Display control function
FL: (35 to
43)
segments
×
(18 to
10)
digits
16
levels dimmer function
Light-and-dark
2-tones
display function
Can support automatic display to universal grid display tubes
Output dimmer waveform for FL driver connection (DROUT)
Internal pull down resister is available between Port
6
and Vpp, Port
9
and Vpp, Port B and Vpp, Port C and Vpp, Port D and Vpp by
Mask option (only for Mask ROM version)
Internal pull down resister between Port
4
and Vpp, Port
7
and Vpp, Port
8
and Vpp
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