Preliminary
Datasheet
RJK0202DSP
Silicon N Channel Power MOS FET
Power Switching
Features
High speed switching
Capable of 2.5 V gate drive
Low drive current
High density mounting
Low on-resistance
R
DS(on)
= 5.0 m
typ. (at V
GS
= 4.5 V)
R07DS0238EJ0220
Rev.2.20
Jan 05, 2011
Outline
RENESAS Package code: PRSP0008DD-D
(Package name: SOP-8<FP-8DAV>)
5
76
4
4
G
5 6 7 8
D D D D
1, 2, 3
Source
4
Gate
5, 6, 7, 8 Drain
8
3
12
S S S
1 2 3
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel to ambient thermal impedance
Channel temperature
Storage temperature
Symbol
V
DSS
V
GSS
I
D
I
D(pulse)
I
DR
I
AP Note 2
E
AR Note 2
Pch
Note3
ch-a
Note3
Tch
Tstg
Note1
Ratings
20
±12
16
128
16
15
45
2.0
62.5
150
–55 to +150
Unit
V
V
A
A
A
A
mJ
W
C/W
C
C
Notes: 1. PW
10
s,
duty cycle
1%
2. Value at Tch = 25C, Rg
50
3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW
10s
R07DS0238EJ0220 Rev.2.20
Jan 05, 2011
Page 1 of 6
RJK0202DSP
Preliminary
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Gate Resistance
Total gate charge
Gate to source charge
Gate to drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body–drain diode forward voltage
Body–drain diode reverse recovery
time
Notes: 4. Pulse test
Symbol
V
(BR)DSS
I
GSS
I
DSS
V
GS(off)
R
DS(on)
R
DS(on)
|y
fs
|
Ciss
Coss
Crss
Rg
Qg
Qgs
Qgd
t
d(on)
t
r
t
d(off)
t
f
V
DF
t
rr
Min
20
—
—
0.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
5.0
6.2
55
3650
640
330
1.4
31
6.2
6.9
20
40
72
18
0.75
50
Max
—
± 0.1
1
1.4
6.3
8.7
—
—
—
—
—
—
—
—
—
—
—
—
0.98
—
Unit
V
A
A
V
m
m
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
V
ns
Test Conditions
I
D
= 10 mA, V
GS
= 0
V
GS
= ±12 V, V
DS
= 0
V
DS
= 20 V, V
GS
= 0
V
DS
= 10 V, I
D
= 1 mA
I
D
= 8 A, V
GS
= 4.5 V
Note4
I
D
= 8 A, V
GS
= 2.5 V
Note4
I
D
= 8 A, V
DS
= 10 V
Note4
V
DS
= 10 V
V
GS
= 0
f = 1 MHz
V
DD
= 10 V
V
GS
= 4.5 V
I
D
= 16 A
V
GS
= 4.5 V, I
D
= 8 A
V
DD
10 V
R
L
= 1.25
Rg = 4.7
IF = 16 A, V
GS
= 0
Note4
IF = 16 A, V
GS
= 0
di
F
/ dt = 100 A/
s
R07DS0238EJ0220 Rev.2.20
Jan 05, 2011
Page 2 of 6
RJK0202DSP
Preliminary
Main Characteristics
Power vs. Temperature Derating
4.0
500
Test Condition :
When using the glass epoxy board
(FR4 40x40x1.6 mm), PW < 10 s
3.0
10
μs
Maximum Safe Operation Area
Channel Dissipation Pch (W)
100
Drain Current I
D
(A)
10
DC
PW
Op
era
tio
10
=1
1m
0
μ
s
0m
s
2.0
n(
s
1
PW
1.0
0.1
Operation in
this area is
limited by R
DS(on)
Ta = 25°C
1 shot Pulse
0.3
1
3
N
< 1
ote
0s
5
)
0
50
100
150
200
0.01
0.1
10
30
100
Ambient Temperature Ta (°C)
Drain to Source Voltage V
DS
(V)
Note 5 : When using the glass epoxy board
(FR4 40x40x1.6 mm)
Typical Output Characteristics
20
10, 4.5 V
Pulse Test
Typical Transfer Characteristics
20
V
DS
= 10 V
Pulse Test
Drain Current I
D
(A)
12
1.4 V
Drain Current I
D
(A)
16
1.5 V
16
12
8
Tc = 75°C
8
4
V
GS
= 1.3 V
4
25°C
–25°C
0
2
4
6
8
10
0
1
2
3
4
5
Drain to Source Voltage V
DS
(V)
Gate to Source Voltage V
GS
(V)
Static Drain to Source on State Resistance
vs. Drain Current
Drain to Source on State Resistance
R
DS(on)
(mΩ)
100
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source Voltage V
DS(on)
(mV)
200
Pulse Test
160
Pulse Test
50
20
10
5
120
V
GS
= 2.5 V
80
I
D
= 10 A
40
4.5 V
2
1
1
10
100
1000
5A
2A
0
4
8
12
16
20
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
R07DS0238EJ0220 Rev.2.20
Jan 05, 2011
Page 3 of 6
RJK0202DSP
Static Drain to Source on State Resistance
vs. Temperature
12
10000
Preliminary
Typical Capacitance vs.
Drain to Source Voltage
Static Drain to Source on State Resistance
R
DS(on)
(m)
Pulse Test
I
D
= 2A, 5A,10 A
Ciss
Capacitance C (pF)
10
3000
1000
300
8
Coss
V
GS
= 2.5 V
6
Crss
100
30
10
2 A, 5 A, 10 A
4
2
-25
4.5 V
V
GS
= 0
f = 1 MHz
0
5
10
15
20
25
30
0
25
50
75
100 125 150
Case Temperature
Tc
(°C)
Drain to Source Voltage V
DS
(V)
Dynamic Input Characteristics
Reverse Drain Current vs.
Source to Drain Voltage
Drain to Source Voltage V
DS
(V)
Gate to Source Voltage V
GS
(V)
50
40
30
20
Reverse Drain Current I
DR
(A)
I
D
= 16 A
20
16
12
8
20
16
10 V
V
GS
= 0 V
V
DD
= 10 V
5V
V
GS
12
8
V
DS
10
V
DD
= 10 V
5V
4
0
100
4
Pulse Test
0
0.4
0.8
1.2
1.6
2.0
0
20
40
60
80
Gate Charge Qg (nc)
Source to Drain Voltage V
SD
(V)
Maximum Avalanche Energy vs.
Channel Temperature Derating
Repetitive Avalanche Energy E
AR
(mJ)
50
40
I
AP
= 15 A
V
DD
= 15 V
duty < 0.1 %
Rg > 50
30
20
10
0
25
50
75
100
125
150
Channel Temperature Tch (°C)
R07DS0238EJ0220 Rev.2.20
Jan 05, 2011
Page 4 of 6
RJK0202DSP
Normalized Transient Thermal Impedance vs. Pulse Width
10
Preliminary
Normalized Transient Thermal Impedance
γs
(t)
1
D=1
0.5
0.1
0.2
0.1
0.05
0.01
0.02
0.01
0.001
1s
h
p
ot
uls
e
θch
- f(t) =
γs
(t) x
θch
- f
θch
- f = 100°C/ W, Ta = 25°C
When using the glass epoxy board
(FR4 40 x 40 x 1.6 mm)
PDM
PW
T
D=
PW
T
0.0001
1
μ
10
μ
1m
10 m
100 m
1
10
100
1000
10000
Pulse Width PW (s)
Avalanche Test Circuit
E
AR
=
Avalanche Waveform
1
2
L
•
I
AP
2
•
V
DSS
V
DSS
- V
DD
V
DS
Monitor
L
I
AP
Monitor
V
(BR)DSS
I
AP
V
DD
I
D
V
DS
Rg
Vin
D. U. T
50
Ω
0
V
DD
Switching Time Test Circuit
Vin Monitor
Rg
D.U.T.
R
L
V
DS
= 10 V
Vin
Vout
Vin
Vout
Monitor
Switching Time Waveform
90%
10%
10%
90%
td(on)
tr
90%
td(off)
tf
10%
R07DS0238EJ0220 Rev.2.20
Jan 05, 2011
Page 5 of 6
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