NJW4180
High Voltage Low current consumption Regulator
GENERAL DESCRIPTION
The NJW4180 is a high voltage and low current consumption
linear
regulator.
Low current consumption make the NJW4180 possible to supply
2.5 to 5.0 V regulated voltage from high voltage input.
Therefore, it is suitable for a power supply for micro controllers,
battery related applications, LED and other applications where
low power consumption is essential.
PACKAGE OUTLINE
NJW4180KG1
NJW4180F
FEATURES
•
Operating Voltage Range
•
Low Current Consumption
•
MLCC correspond
•
Output Current
•
High Precision Output
•
Internal Thermal Overload Protection
•
Internal Over Current Protection
•
Internal Reverse Current Protection
•
Package Outline
PIN CONNECTION
PIN CONFIGURATION
1. N.C.
2. GND
NJW4180
3. N.C.
4. V
IN
1
2
3
5. N.C.
6. V
OUT
NJW4180KG1
6
5
4
35V (max.)
9µA (typ.)
I
O
(min.)=20mA
V
O
±1.5%
ESON6-G1, SOT23-5
5
4
1 2 3
NJW4180F
PIN CONFIGURATION
1. N.C.
2. GND
3. N.C.
4. V
OUT
5. V
IN
BLOCK DIAGRAM
VIN
Current
Limit
VOUT
Thermal
Protection
Bandgap
Reference
GND
Ver.2011-01-27
-1-
NJW4180
OUTPUT VOLTAGE LANK LIST
Device Name
V
OUT
NJW4180F25
2.5V
NJW4180F33
3.3V
NJW4180F05
5.0V
Device Name
NJW4180KG1-25
NJW4180KG1-33
NJW4180KG1-05
V
OUT
2.5V
3.3V
5.0V
(Ta=25°C)
RATINGS
UNIT
+40
V
+7
V
330 (*1)
ESON6-G1
905 (*2)
Power Dissipation
P
D
mW
390 (*3)
SOT-23-5
520 (*4)
Operating Temperature
Topr
-40 to +85
°C
Storage Temperature
Tstg
-50 to +125
°C
(*1): Mounted on glass epoxy board based on EIA/JEDEC STANDARD.
(101.5×114.5×1.6mm: 2Layers with Exposed Pad FR-4)
(*2): Mounted on glass epoxy board based on EIA/JEDEC STANDARD.
(101.5×114.5×1.6mm: 4Layers with Exposed Pad FR-4, Internal foil area size: 99.5×99.5mm, Applying a thermal via
hole to a board based on JEDEC standard JESD51-5)
(*3): Mounted on glass epoxy board based on EIA/JEDEC. (114.3×76.2×1.6mm: 2Layers FR-4)
(*4): Mounted on glass epoxy board based on EIA/JEDEC. (114.3×76.2×1.6mm: 4Layers FR-4)
PROTECTION CIRCUIT
Over Current Protection
Thermal Shutdown
Reverse Current Protection
INPUT VOLTAGE RANG
V
O
≤3V:
V
IN
= +5.5V to +35V
V
O
>3V:
V
IN
= V
O
+2.5V to +35V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYNBOL
Input Voltage
V
IN
Output Voltage
V
OUT
-2-
Ver.2011-01-27
NJW4180
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, V
IN
=Vo+2.5V (Vo≤3V: V
IN
=5.5V), C
IN
=0.1 µF, C
O
=1µF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Output Voltage
V
O
I
O
=10mA
-1.5%
-
+1.5%
V
Quiescent Current
I
Q
I
O
=0mA
-
9
15
µA
20
30
-
mA
Output Current
Io
V
O
×
0.9
V
IN
= 5.5V to 35V, I
O
=10mA (V
O
≤3V
)
Line Regulation
-
0.02
0.05
%/V
∆V
O
/∆V
IN
V
IN
= V
O
+2.5V to 35V, I
O
=10mA (V
O
>3V
)
I
O
=0mA to 20mA
Load Regulation
-
0.005
0.02
%/mA
∆V
O
/∆I
O
Average Temperature
-
-
Coefficient of
±
100
ppm/°C
∆V
O
/∆Ta Ta=0 to 85°C, I
O
=10mA
Output Voltage
Sink Current
under
I
REVERSE
Reverse Current
V
IN
= 0V, V
O
= 5V
-
50
75
µA
Protection
operating
5.5
-
35
V
O
≤3V
V
Input Voltage
V
IN
V
O
+2.5
-
35
V
O
>3V
The above specification is a common specification for all output voltages.
Therefore, it may be different from the individual specification for a specific output voltage.
Ver.2011-01-27
-3-
NJW4180
POWER DISSIPATION vs. AMBIENT TEMPERATURE
NJW4180KG1 Power Dissipation
(Topr=-40~+85°C,Tj=125°C)
1000
800
Power Dissipation PD(mW)
on 4 layers board
(101.5×114.5×1.6mm)
600
400
on 2 layers board
(101.5×114.5×1.6mm)
200
0
-50
-25
0
25
50
75
100
Temperature Ta(°C)
NJW4180F Power Dissipation
(Topr=-40~+85°C,Tj=125°C)
800
700
Power Dissipation PD(mW)
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100
Temperature Ta(°C)
on 2 layers board
(114.3×76.2×1.6mm)
on 4 layers board
(114.3×76.2×1.6mm)
-4-
Ver.2011-01-27
NJW4180
TEST CIRCUIT
I
IN
V
IN
V
OUT
A
V
IN
NJW4180
I
OUT
0.1µF
GND
1µF
(ceramic)
V
V
OUT
TYPICAL APPLICATION
V
IN
V
IN
V
OUT
V
OUT
NJW4180
0.1µF
GND
1µF
*Input Capacitance C
IN
Input Capacitance (C
IN)
) is required to prevent oscillation and reduce power supply ripple for applications with high
power supply impedance or a long power supply line.
Use the C
IN
value of 0.1µF greater to avoid the problem.
C
IN
should connect between GND and V
IN
as short as possible.
*Output Capacitance C
O
Output capacitor (C
O
) is required for a phase compensation of the internal error amplifier. The capacitance and the
equivalent series resistance (ESR) influences stability of the regulator.
This product is designed to work with a low ESR capacitor for the C
O
; however, use of recommended capacitance or
greater value is essential for stable operation.
Use of a smaller C
O
may cause excess output noise or oscillation of the regulator due to lack of the phase
compensation.
Therefore, use C
O
with the recommended capacitance or greater value and connect between V
O
terminal and
GND terminal with minimal wiring. The recommended capacitance depends on the output voltage. Low voltage
regulator requires greater value of the C
O
. Thus, check the recommended capacitance for each output voltage.
Use of a greater C
O
reduces output noise and ripple output, and also improves transient response of the output
voltage against rapid load change.
Ver.2011-01-27
-5-
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
