NCP4629
Product Preview
500 mA, Wide Input Range,
LDO Linear Voltage
Regulator
The NCP4629 is a CMOS 500 mA LDO linear voltage regulator
which features a high input voltage range while maintaining a low
quiescent current. Several protection features like current limiting and
thermal shutdown are fully integrated to create a versatile and robust
device. A high maximum input voltage (36 V) and wide temperature
range (−40°C to 105°C) makes the NCP4629 an ideal choice for high
power industrial applications.
Features
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MARKING
DIAGRAMS
XXXXXXXX
XX
MM
DPAK−5
CASE 369AE
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 4 V to 24 V
Output Voltage Range: 3.0 to 12.0 V (available in 0.1 V steps)
±2%
Output Voltage Accuracy
Output Current: min. 500 mA (V
IN
= V
OUT
+ 1 V)
Line Regulation: 0.05%/V
Current Limit Circuit
Thermal Shutdown Circuit
Available in SOT−89−5 and DPACK5 Package
These are Pb−Free Devices
1
1
SOT−89 5
CASE 528AB
XXX
XMM
Typical Applications
Home appliances, industrial equipment
Cable boxes, satellite receivers, entertainment systems
Car audio equipment, navigation systems
Notebook adaptors, LCD TVs, cordless phones and private LAN
systems
•
Office equipment: copiers, printers, facsimiles, scanners, projectors,
monitors
VIN
C1
470 n
NCP4629x
VIN
CE
VOUT
GND
VOUT
C2
10m
XX, XXX= Specific Device Code
M, MM = Date Code
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 1. Typical Application Schematic
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2010
December, 2010
−
Rev. P1
1
Publication Order Number:
NCP4629/D
NCP4629
VIN
VOUT
Vref
CE
Current Limit
Short Protection
Thermal Shutdown
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOT89
1
2
3
4
5
Pin No.
DPACK
1
2
3
4
5
Pin Name
VIN
GND
GND
CE
VOUT
Input pin
Ground pin, all ground pins must be connected together when it is
mounted on board
Ground pin, all ground pins must be connected together when it is
mounted on board
Chip enable pin (“H” active)
Output pin
Description
ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage
Output Voltage
Chip Enable Input
Power Dissipation SOT−89
Power Dissipation DPACK
Junction Temperature
Storage Temperature
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
T
J
T
STG
ESD
HBM
ESD
MM
Symbol
V
IN
V
OUT
V
CE
P
D
Value
−0.3
to 36
−0.3
to V
IN
≤
36
−0.3
to V
IN
≤
36
900
1900
−40
to 150
−55
to 125
2000
200
°C
°C
V
V
Unit
V
V
V
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Duration time = 200 ms
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latch−up Current Maximum Rating tested per JEDEC standard: JESD78.
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2
NCP4629
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, SOT−89
Thermal Resistance, Junction−to−Air
Thermal Characteristics, DPACK
Thermal Resistance, Junction−to−Air
Symbol
R
qJA
R
qJA
Value
111
53
Unit
°C/W
°C/W
ELECTRICAL CHARACTERISTICS
T
A
= 25°C
Parameter
Operating Input Voltage
Output Voltage
Output Voltage Temp.
Coefficient
Line Regulation
Load Regulation
Dropout Voltage
V
IN
= V
OUT
+ 1 V, I
OUT
= 100 mA
V
IN
= V
OUT
+ 2 V, I
OUT
= 100
mA,
T
A
=
−40
to
105°C
V
IN
= V
OUT
+ 1 V to 24 V, I
OUT
= 10 mA
V
IN
= V
OUT
+ 2 V, I
OUT
= 0.1 mA to 200 mA
I
OUT
= 200 mA
3.0 V
≤
V
OUT
< 5.0 V
5.0 V
≤
V
OUT
< 9.0 V
8.0 V
≤
V
OUT
≤
12.0 V
Output Current
Short Current Limit
Quiescent Current
Standby Current
CE Pin Threshold Voltage
V
IN
= V
OUT
+ 1 V
V
OUT
= 0 V
V
IN
= V
OUT
+ 1 V, V
IN
= V
CE
V
IN
= 24 V, V
CE
= 0 V
CE Input Voltage “H”
CE Input Voltage “L”
Thermal Shutdown Temperature
Thermal Shutdown Release
Temperature
Power Supply Rejection Ratio
V
IN
= V
OUT
+ 2.0 V,
ΔV
IN_PK−PK
= 0.5 V,
I
OUT
= 100 mA, f =
1 kHz
V
OUT
≤
6.0 V
V
OUT
> 6.0 V
V
N
I
OUT
I
SC
I
Q
I
STB
V
CEH
V
CEL
T
SD
T
SR
PSRR
2.0
0
160
135
60
50
TBD
mV
rms
500
65
70
0.1
130
1
V
IN
0.4
°C
°C
dB
Line
Reg
Load
Reg
V
DO
Test Conditions
Symbol
V
IN
V
OUT
Min
4
x0.98
±100
0.05
25
0.135
0.115
0.095
0.10
60
0.225
0.180
0.155
mA
mA
mA
mA
V
Typ
Max
24
x1.02
Unit
V
V
ppm/°C
%/V
mV
V
Output Noise Voltage
V
OUT
= TBD V, I
OUT
= TBD mA, f = 10 Hz to
100 kHz
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3
NCP4629
APPLICATION INFORMATION
A typical application circuit for NCP4629 series is shown
in Figure 3.
VIN
C1
470 n
NCP4629x
VIN
CE
GND
VOUT
C2
10
m
VOUT
Output Decoupling Capacitor (C2)
A 10
mF
ceramic output decoupling capacitor is sufficient
to achieve stable operation of the IC. If tantalum capacitor
is used, and its ESR is high, the loop oscillation may result.
The capacitor should be connected as close as possible to the
output and ground pin. Larger values and lower ESR
improves dynamic parameters.
Enable Operation
Figure 3. Typical Application Schematic
The enable pin CE may be used for turning the regulator
on and off. The IC is switched on when a high level voltage
is applied to the CE pin. The enable pin has an internal pull
down current source. If the enable function is not needed
connect CE pin to VIN.
Thermal
When VOUT voltage could be higher than VIN voltage it
is necessary to use protective diode D1. If there is possibility
that VOUT voltage could be negative then it is necessary to
use schottky diode D2. See Figure 4 for details. Do not force
the voltage to the VOUT pin.
D1
NCP4629x
VIN
C1
470 n
CE
VOUT
GND
C2
10
m
D2
VIN
VOUT
As a power across the IC increase, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature increase for the
part. When the device has good thermal conductivity
through the PCB the junction temperature will be relatively
low in high power dissipation applications.
The IC includes internal thermal shutdown circuit that
stops operation of regulator, if junction temperature is
higher than 160°C. After that, when junction temperature
decreases below 135°C, the operation of voltage regulator
would restart. While high power dissipation condition is, the
regulator starts and stops repeatedly and protects itself
against overheating.
PCB layout
Figure 4. Typical Application Schematic with
Protective Diodes
Input Decoupling Capacitor (C1)
A 470 nF ceramic input decoupling capacitor should be
connected as close as possible to the input and ground pin of
the NCP4629. Higher values and lower ESR improves line
transient response.
ORDERING INFORMATION
Device
NCP4629HDT050T5G
NCP4629HDT060T5G
NCP4629HDT120T5G
Nominal Output
Voltage
5.0 V
6.0 V
12.0 V
Description
Enable High
Enable High
Enable High
Pins number 2 and 3 must be wired to the GND plane
while it is mounted on board. Make VIN and GND lines
sufficient. If their impedance is high, noise pickup or
unstable operation may result. Connect capacitors C1 and
C2 as close as possible to the IC, and make wiring as short
as possible.
Marking
C1J050B
C1J060B
C1J120B
Package
DPACK−5
(Pb−Free)
DPACK−5
(Pb−Free)
DPACK−5
(Pb−Free)
Shipping
†
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*To order other package and voltage variants, please contact your ON Semiconductor sales representative.
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4
NCP4629
PACKAGE DIMENSIONS
DPAK−5 (TO−252, 5 LEAD)
CASE 369AE−01
ISSUE O
C
A
c2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. THERMAL PAD CONTOUR OPTIONAL, WITHIN
DIMENSIONS b3, E2, L3 AND Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15mm PER SIDE. THESE
DIMENSIONS TO BE MEASURED AT DATUM H.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
DIM
A
A1
b
b2
c
c2
D
E
E2
e
H
L
L1
L2
L3
Z
MILLIMETERS
MIN
MAX
2.10
2.50
0.00
0.13
0.40
0.60
5.14
5.54
0.40
0.60
0.40
0.60
5.90
6.30
6.40
6.80
5.04 REF
1.27 BSC
9.60
10.20
1.39
1.78
2.50
2.90
0.51 BSC
0.90
1.30
2.74 REF
E
b2
A
B
L3
D
DETAIL A
1
2 3
4
5
Z
H
E2
e
b
TOP VIEW
0.12
M
c
SIDE VIEW
C A B
BOTTOM VIEW
H
C
L
L1
DETAIL A
0.10 C
A1
L2
GUAGE
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
5.70
6.00
10.50
5X
2.10
5X
0.80
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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