shielding effect differs depending on the wire specifications.
* Compliant with RoHS.
* Refer to "General Instruction and Notice when using
Terminals and Connectors" at the end of this catalog.
* Contact JST for details.
PC board layout
Layout
Mating section layout
Circuits
Standard and Type B
2.5
±0.05
6.8
±0.1
φ0.9
＋0.1
0
PC board layout
(viewed from component side)
Front shielding type
2.5
±0.05
3.0
±0.05
φ2.2
±0.1
8.5
max.
2.5
±0.05
8.5
max.
2.5
±0.05
8.5
max.
6.8
±0.1
φ0.9
＋0.1
0
4
2
4
3
3
1
2.4
±0.1
0.8
±0.1
0.8
±0.1
4
2
3
1
3.0
±0.05
φ2.2
±0.1
Note
13.5
±0.1
Receptacle mating
side surface
2.2
±0.1
8.5
max.
4
2
1
3.8
±0.05
3.0
±0.05
13.5
±0.1
Hole dimensions (from the front)
Receptacle mating
side surface
2.5
5
5
4
2
1
1.3
±0.05
±0.05
6.8
±0.1
φ0.9
＋0.1
0
6.8
±0.1
φ0.9
＋0.1
0
4
2
0.8
±0.1
0.8
±0.1
5
3
1
4
2
1.3
±0.05
φ2.2
±0.1
3.0
±0.05
φ0.9
＋
0.1
0
3
3.8
±0.05
1
2.4
±0.1
Note
13.5
±0.1
Receptacle mating
side surface
2.2
±0.1
8.5
max.
5
3
3.0
±0.05
13.5
±0.1
Hole dimensions (from the front)
Receptacle mating
side surface
6.8
±0.1
2.5
±0.05
φ0.9
＋0.1
0
6.8
±0.1
6
4
6
5
2.6
±0.05
5
3
0.8
±0.1
0.8
±0.1
6
4
2
1
2.6
±0.05
5
3
2
1
2.4
±0.1
2
1
Note
13.5
±0.1
Receptacle mating
side surface
2.2
±0.1
8.5
max.
6
3.0
4
3
3.8
±0.05
±0.05
13.5
±0.1
Hole dimensions (from the front)
Receptacle mating
side surface
1
MD CONNECTOR
Layout
Mating section layout
Circuits
Standard and Type B
Front shielding type
PC board layout
(viewed from component side)
6.8
±0.1
2.6
±0.05
φ0.9
＋0.1
0
2.5
±0.05
3.0
±0.05
2.2
±0.1
8.5max.
0.9
±0.05
7
7
6
5
3
2
1
6
2
1
2.4
±0.1
5
3
0.8
±0.1
0.8
±0.1
4
3.8
±0.05
Note
7
4
13.5
±0.1
Receptacle mating
side surface
8
5
2
4
7
6
3
1
6.8
±0.1
2.6
±0.05
±0.05
6.8
±0.1
φ0.9
＋0.1
0
0.9
±0.05
0.1
φ0.9
＋0
0.9
±0.05
2.5
8
5
3.8
±0.05
7
2
4
1
2.4
±0.1
6
3
0.8
±0.1
0.8
±0.1
8
5
7
2
4
1
2.6
±0.05
6
3
3.0
±0.05
φ2.2
±0.1
8
8
7
5
2
4
1
6
Note
3
2.2
±0.1
8.5max.
13.5
±0.1
Receptacle mating
side surface
13.5
±0.1
Hole dimensions (from the front)
Receptacle mating
side surface
8.0
±0.1
4.0
±0.1
2.5
±0.05
2.0
±0.05
φ0.9
＋0.1
0
9
9
6
8
5
2
4
1
7
3
8
5
4
7
0.7
±0.05
3.8
±0.05
1.3
±0.05
0.8
±0.1
3.0
±0.05
6
2
1
2.4
±0.1
3
0.8
±0.1
2.2
±0.1
9
Note
13.5
±0.1
Receptacle mating
side surface
Note: 1. The two holes are necessary when installing a shielding cover.
2. Tolerances are non-cumulative:
±
0.05mm for all centers.
3. Hole dimensions differ depending on the kind of PC board and piercing method. The dimensions above should serve as a guideline.
For details, contact JST.
4. The layout drawing is viewed from the receptacle mounting side.
5. When using a receptacle with shielding cover or with flange shielding cover, the pattern should be designed to connect the shielding cover and the shielding
tube, if necessary. (No need for the front shielding cover.)
FPGA/CPLD
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