SSD20N10-250D
Elektronische Bauelemente
N-Ch Enhancement Mode Power MOSFET
11A, 100V, R
DS(ON)
280mΩ
RoHS Compliant Product
A suffix of “-C” specifies halogen free
DESCRIPTION
These miniature surface mount MOSFETs utilize a high cell density trench
process to provide Low R
DS(on)
and to ensure minimal power loss and heat dissipation.
Typical applications are DC-DC converters and power management in portable
and battery-powered products such as computers, printers, PCMCIA cards, cellular
and cordless telephones.
TO-252(D-Pack)
FEATURES
Low R
DS(on)
provides higher efficiency and extends battery life.
Low thermal impedance copper leadframe DPAK saves board space.
Fast switching speed.
High performance trench technology.
A
B
C
D
PRODUCT SUMMARY
V
DS
(V)
100
PRODUCT SUMMARY
R
DS
(on) m(
280@V
GS
= 10V
355@V
GS
= 4.5V
I
D
(A)
11
10
GE
K
HF
Drain
M
J
N
O
P
Gate
REF.
Source
A
B
C
D
E
F
G
H
Millimeter
Min.
Max.
6.4
6.8
5.20
5.50
2.20
2.40
0.45
0.58
6.8
7.3
2.40
3.0
5.40
6.2
0.8
1.20
REF.
J
K
M
N
O
P
Millimeter
Min.
Max.
2.30 REF.
0.70
0.90
0.50
1.1
0.9
1.6
0
0.15
0.43
0.58
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
a
Pulsed Drain Current
b
Continuous Source Current (Diode Conduction)
a
Total Power Dissipation
a
Operating Junction and Storage Temperature Range
Maximum Thermal Resistance Junction-Ambient
a
Maximum Thermal Resistance Junction-Case
Notes：
a. Surface Mounted on 1” x 1” FR4 Board.
b. Pulse width limited by maximum junction temperature.
UNIT
V
V
A
A
A
W
°C
°C / W
°C / W
V
DS
V
GS
I
D
@T
C
=25℃
I
DM
I
S
P
D
@T
C
=25℃
T
J
, T
STG
R
θJA
R
θJC
100
±20
11
36
30
50
-55 ~ 175
50
3.0
THERMAL RESISTANCE RATINGS
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
11-Aug-2010 Rev.A
Page 1 of 2
SSD20N10-250D
Elektronische Bauelemente
N-Ch Enhancement Mode Power MOSFET
11A, 100V, R
DS(ON)
280mΩ
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
PARAMETER
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-Resistance
Forward Transconductance
a
Diode Forward Voltage
a
SYMBOL MIN. TYP. MAX. UNIT
Static
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(ON)
g
fs
V
SD
1.0
-
-
-
34
-
-
-
-
-
-
-
-
-
-
-
5
1
-
±100
1
25
-
280
355
-
-
V
nA
μA
A
mΩ
S
V
TEST CONDITIONS
V
DS
= V
GS,
I
D
= 250
μA
V
DS
= 0V, V
GS
= 20V
V
DS
= 80V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
=55°C
V
DS
= 5V, V
GS
= 10V
V
GS
= 10V, I
D
= 4.5 A
V
GS
= 4.5V, I
D
= 4 A
V
DS
= 15V, I
D
= 4.5 A
I
S
= 9 A, V
GS
= 0 V
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
T
d(on)
T
r
T
d(off)
T
f
-
-
-
-
-
-
-
10
2
7.8
4.8
4
12.8
4
-
-
-
-
-
-
-
nS
V
DD
= 50 V
I
D
= 4.5 A
V
GEN
= 10 V
R
L
= 11.1
nC
V
DS
= 50 V
V
GS
= 5.5 V
I
D
= 4.5 A
Notes
a. Pulse test：Pulse width
≦
300
μs,
duty cycle
≦
2％.
b. Guaranteed by design, not subject to production testing.
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
11-Aug-2010 Rev.A
Page 2 of 2
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