CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
A
= +25
o
C, V+ = 15V, V- = 0V (Unless Otherwise Specified)
LIMITS
CA3130A
CA3130
MAX
5
20
30
-
-
-
MIN
-
-
-
50
94
70
TYP
8
0.5
5
320
110
90
MAX
15
30
50
-
-
-
UNITS
mV
pA
pA
kV/V
dB
dB
TEST
CONDITIONS
V± =
±7.5V
V± =
±7.5V
V± =
±7.5V
V
O
= 10 Vp-p
R
L
= 2kΩ
PARAMETERS
Input Offset Voltage
Input Offset Current
Input Current
Large-Signal Voltage Gain
SYMBOLS
|V
IO
|
|I
IO
|
I
I
A
OL
MIN
-
-
-
50
94
80
TYP
2
0.5
5
320
110
90
Common-Mode
Rejection Ratio
Common-Mode Input
Voltage Range
Power-Supply
Rejection Ratio
Maximum Output Voltage
CMRR
V
ICR
∆V
IO
/∆V±
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V± =
±7.5V
0
-0.5 to
12
32
10
0
-0.5 to
12
32
10
V
µV/V
-
150
-
320
At R
L
= 2kΩ
At R
L
= 2kΩ
At R
L
= 2kΩ
At R
L
= 2kΩ
12
-
14.99
-
12
12
-
13.3
0.002
15
0
22
20
10
-
0.01
-
0.01
45
45
15
12
-
14.99
-
12
12
-
13.3
0.002
15
0
22
20
10
-
0.01
-
0.01
45
45
15
V
V
V
V
mA
mA
mA
Maximum Output Current
I
OM
+ (Source) at V
O
= 0V
I
OM
- (Sink) at V
O
= 15V
Supply Current
I+
V
O
= 7.5V,
R
L
=
∞
V
O
= 0V,
R
L
=
∞
I+
∆V
IO
/∆T
-
2
3
-
2
3
mA
µV/
o
C
Input Offset Voltage
Temperature Drift
NOTE:
-
10
-
-
10
-
1. Short circuit may be applied to ground or to either supply.
2-109
Specifications CA3130, CA3130A
Electrical Specifications
Typical Values Intended Only for Design Guidance, V+ = +7.5V, V- = -7.5V, T
A
= +25
o
C
(Unless Otherwise Specified)
CA3130A,
CA3130
±22
PARAMETERS
Input Offset Voltage Adjustment Range
SYMBOL
TEST CONDITIONS
10kΩ Across Terms. 4 and 5 or
4 and 1
UNITS
mV
Input Resistance
Input Capacitance
Equivalent Input Noise Voltage
Unity Gain Crossover Frequency
R
I
C
I
e
N
f = 1MHz
BW = 0.2MHz, R
S
= 1MΩ*
C
C
= 0
f
T
C
C
= 47pF
1.5
4.3
23
15
4
TΩ
pF
µV
MHz
MHz
Slew Rate:
Open Loop
Closed Loop
Transient Response:
Rise Time
Overshoot
Settling Time (To <0.1%, V
IN
= 4V
P-P
)
SR
C
C
= 0
C
C
= 56pF
C
C
= 56pF,
C
L
= 25pF,
R
L
= 2kW
(Voltage Follower)
30
10
V/µs
V/µs
t
R
OS
t
S
0.09
10
1.2
µs
%
µs
* Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of R
S
up to 10MΩ.
Electrical Specifications
PARAMETERS
Input Offset Voltage
Input Offset Current
Input Current
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T
A
= +25
o
C
(Unless Otherwise Specified)
SYMBOL
V
IO
I
IO
I
I
CMRR
A
OL
V
O
= 4V
P-P
, R
L
= 5kW
TEST CONDITIONS
CA3130A
2
0.1
2
90
100
100
CA3130
8
0.1
2
80
100
100
0 to 2.8
300
500
200
UNITS
mV
pA
pA
dB
kV/V
dB
V
µA
µA
µV/V
Common-Mode Input Voltage Range
Supply Current
V
ICR
I+
V
O
= 5V, R
L
=
∞
V
O
= 2.5V, R
L
=
∞
0 to 2.8
300
500
200
Power Supply Rejection Ratio
∆V
IO
/∆V+
2-110
CA3130, CA3130A
CURRENT SOURCE FOR
Q6 AND Q7
“CURRENT SOURCE
LOAD” FOR Q11
7
V+
BIAS CIRCUIT
Q1
D1
Z1
8.3V
R1
40kΩ R2
5kΩ
D2
D3
D4
Q2
Q3
Q4
Q5
SECOND
STAGE
INPUT STAGE
NON-INV.
INPUT
+
INV.-INPUT
2
-
3
D5
D6
D7
D8
OUTPUT
STAGE
Q8
OUTPUT
6
Q6
Q7
R3
1kΩ
Q9 Q10
R4
1kΩ
Q12
Q11
R5
1kΩ
R6
1kΩ
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
V-
NOTE: DIODES D5 THROUGH D8 PROVIDE GATE-OXIDE
PROTECTION FOR MOSFET INPUT STAGE
FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3130 SERIES
Circuit Description
Figure 2 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5 V below the negative supply rail, and the output
can be swung very close to either supply rail in many appli-
cations. Consequently, the CA3130 Series circuits are ideal
for single-supply operation. Three Class A amplifier stages,
having the individual gain capability and current consump-
tion shown in Figure 2, provide the total gain of the CA3130.
A biasing circuit provides two potentials for common use in
the first and second stages. Term. 8 can be used both for
phase compensation and to strobe the output stage into qui-
escence. When Term. 8 is tied to the negative supply rail
(Term. 4) by mechanical or electrical means, the output
potential at Term. 6 essentially rises to the positive supply-
rail potential at Term. 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g.,when the
amplifier output is used to drive CMOS digital circuits in
Comparator applications).
Input Stages
The circuit of the CA3130 is shown in Figure 1. It consists of
a differential-input stage using PMOS field-effect transistors
(Q6, Q7) working into a mirror-pair of bipolar transistors (Q9,
Q10) functioning as load resistors together with resistors R3
through R6. The mirror-pair transistors also function as a dif-
ferential-to-single-ended converter to provide base drive to
the second-stage bipolar transistor (Q11). Offset nulling,
when desired, can be effected by connecting a 100,000Ω
potentiometer across Terms. 1 and 5 and the potentiometer
slider arm to Term. 4. Cascade-connected PMOS transistors
Q2, Q4 are the constant-current source for the input stage.
The biasing circuit for the constant-current source is subse-
quently described. The small diodes D5 through D8 provide
gate-oxide protection against high-voltage transients, includ-
ing static electricity during handling for Q6 and Q7.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascade-connected load resistance provided by
2-111
CA3130, CA3130A
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply con-
necting a small capacitor between Terms. 1 and 8. A 47-
picofarad capacitor provides sufficient compensation for sta-
ble unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3 volts, resistor
R2 and zener diode Z1 serve to establish a voltage of 8.3 volts
across the series-connected circuit, consisting of resistor R1,
diodes D1 through D4, and PMOS transistor Q1. A tap at the
junction of resistor R1 and diode D4 provides a gate-bias
potential of about 4.5 volts for PMOS transistors Q4 and Q5
with respect to Term. 7. A potential of about 2.2 volts is devel-
oped across diode-connected PMOS transistor Q1 with
respect to Term. 7 to provide gate bias for PMOS transistors
Q2 and Q3. It should be noted that Q1 is “mirror-connected”*
to both Q2 and Q3. Since transistors Q1, Q2, Q3 are
designed to be identical, the approximately 200-microampere
current in Q1 establishes a similar current in Q2 and Q3 as
constant current sources for both the first and second ampli-
fier stages, respectively.
At total supply voltages somewhat less than 8.3 volts, zener
diode Z1 becomes nonconductive and the potential, devel-
oped across series-connected R1, D1-D4, and Q1, varies
directly with variations in supply voltage. Consequently, the
gate bias for Q4, Q5 and Q2, Q3 varies in accordance with
supply-voltage variations. This variation results in deteriora-
tion of the power-supply-rejection ratio (PSRR) at total sup-
ply voltages below 8.3 volts. Operation at total supply
voltages below about 4.5 volts results in seriously degraded
performance.
Output Stage
The output stage consists of a drain-loaded inverting ampli-
fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer charac-
teristics of the output stage for a load returned to the nega-
tive supply rail are shown in Figure 5. Typical op-amp loads
are readily driven by the output stage. Because large-signal
excursions are non-linear, requiring feedback for good wave-
form reproduction, transient delays may be encountered. As
a voltage follower, the amplifier can achieve 0.01 percent
accuracy levels, including the negative supply rail.
* For general information on the characteristics of CMOS transistor-
pairs in linear-circuit applications, see File Number 619, data bulle-
tin on CA3600E “CMOS Transistor Array”.
+
3
INPUT
2
-
V-
4
5
1
C
C
COMPENSATION
(WHEN REQUIRED)
8
STROBE
A
V
≈
5X
A
V
≈
6000X
A
V
≈
30X
OUTPUT
6
CA3130
200µA
1.35mA
200µA
8mA*
0mA**
V+
7
BIAS CKT.
OFFSET
NULL
TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) = 15V
*WITH INPUT TERMINALS BIASED SO THAT TERM. 6 POTENTIAL
IS +7.5V ABOVE TERM. 4.
**WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL.
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