CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
CA3130
CA3130A
MAX
15
-
MIN
-
-
TYP
2
10
MAX
5
-
UNITS
mV
µV/
o
C
TEST
CONDITIONS
V
S
=
±7.5V
PARAMETER
Input Offset Voltage
Input Offset Voltage
Temperature Drift
Input Offset Current
Input Current
Large-Signal Voltage Gain
SYMBOL
|V
IO
|
∆V
IO
/∆T
|I
IO
|
I
I
A
OL
MIN
-
-
TYP
8
10
V
S
=
±7.5V
V
S
=
±7.5V
V
O
= 10V
P-P
R
L
= 2kΩ
-
-
50
94
70
0.5
5
320
110
90
30
50
-
-
-
-
-
50
94
80
0.5
5
320
110
90
20
30
-
-
-
pA
pA
kV/V
dB
dB
Common-Mode
Rejection Ratio
Common-Mode Input
Voltage Range
Power-Supply
Rejection Ratio
Maximum Output Voltage
CMRR
V
ICR
∆V
IO
/∆V
S
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
S
=
±7.5V
R
L
= 2kΩ
R
L
= 2kΩ
R
L
=
∞
R
L
=
∞
0
-0.5 to
12
32
10
0
-0.5 to
12
32
10
V
µV/V
-
320
-
150
12
-
14.99
-
12
12
-
13.3
0.002
15
0
22
20
10
-
0.01
-
0.01
45
45
15
12
-
14.99
-
12
12
-
13.3
0.002
15
0
22
20
10
-
0.01
-
0.01
45
45
15
V
V
V
V
mA
mA
mA
Maximum Output Current
I
OM
+ (Source) at V
O
= 0V
I
OM
- (Sink) at V
O
= 15V
Supply Current
I+
V
O
= 7.5V,
R
L
=
∞
V
O
= 0V,
R
L
=
∞
I+
-
2
3
-
2
3
mA
3-65
CA3130, CA3130A
Electrical Specifications
Typical Values Intended Only for Design Guidance, V
SUPPLY
=
±7.5V,
T
A
= 25
o
C
Unless Otherwise Specified
CA3130,
CA3130A
±22
PARAMETER
Input Offset Voltage Adjustment Range
SYMBOL
TEST CONDITIONS
10kΩ Across Terminals 4 and 5
or 4 and 1
UNITS
mV
Input Resistance
Input Capacitance
Equivalent Input Noise Voltage
R
I
C
I
e
N
f = 1MHz
BW = 0.2MHz, R
S
= 1MΩ
(Note 3)
C
C
= 0
f
T
C
C
= 47pF
1.5
4.3
23
TΩ
pF
µV
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability
≥47pF
Required.)
15
4
MHz
MHz
Slew Rate:
Open Loop
Closed Loop
Transient Response:
Rise Time
Overshoot
Settling Time (To <0.1%, V
IN
= 4V
P-P
)
NOTE:
SR
C
C
= 0
C
C
= 56pF
C
C
= 56pF,
C
L
= 25pF,
R
L
= 2kΩ
(Voltage Follower)
30
10
V/µs
V/µs
t
r
OS
t
S
0.09
10
1.2
µs
%
µs
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of R
S
up to 10MΩ.
Electrical Specifications
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T
A
= 25
o
C
Unless Otherwise Specified (Note 4)
SYMBOL
V
IO
I
IO
I
I
CMRR
A
OL
V
O
= 4V
P-P
, R
L
= 5kΩ
TEST CONDITIONS
CA3130
8
0.1
2
80
100
100
CA3130A
2
0.1
2
90
100
100
0 to 2.8
300
500
200
UNITS
mV
pA
pA
dB
kV/V
dB
V
µA
µA
µV/V
Common-Mode Input Voltage Range
Supply Current
V
ICR
I+
V
O
= 5V, R
L
=
∞
V
O
= 2.5V, R
L
=
∞
0 to 2.8
300
500
200
Power Supply Rejection Ratio
NOTE:
∆V
IO
/∆V+
4. Operation at 5V is not recommended for temperatures below 25
o
C.
3-66
CA3130, CA3130A
Schematic Diagram
BIAS CIRCUIT
CURRENT SOURCE FOR
Q
6
AND Q
7
Q
1
D
1
Z
1
8.3V
R
1
40kΩ R
2
5kΩ
INPUT STAGE
NON-INV.
INPUT
+
INV.-INPUT
2
3
D
5
D
6
(NOTE 5) D
7
D
8
OUTPUT
STAGE
Q
6
Q
7
SECOND
STAGE
D
2
D
3
D
4
Q
4
Q
5
Q
2
“CURRENT SOURCE
LOAD” FOR Q
11
7
V+
Q
3
Q
8
OUTPUT
6
-
R
3
1kΩ
Q
9
Q
10
Q
11
R
5
1kΩ
R
6
1kΩ
R
4
1kΩ
Q
12
5
OFFSET NULL
1
COMPENSATION
8
STROBING
4
V-
NOTE:
5. Diodes D
5
through D
8
provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the out-
put stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentially rises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g.,when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
6
, Q
7
) working into a mirror-pair of bipolar tran-
sistors (Q
9
, Q
10
) functioning as load resistors together with
resistors R
3
through R
6
. The mirror-pair transistors also func-
tion as a differential-to-single-ended converter to provide base
drive to the second-stage bipolar transistor (Q
11
). Offset null-
ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4. Cascade-connected PMOS
transistors Q
2
, Q
4
are the constant-current source for the
input stage. The biasing circuit for the constant-current source
is subsequently described. The small diodes D
5
through D
8
provide gate-oxide protection against high-voltage transients,
including static electricity during handling for Q
6
and Q
7
.
3-67
CA3130, CA3130A
CA3130
200µA
1.35mA
200µA
8mA
(NOTE 5)
0mA
(NOTE 7)
V+
7
BIAS CKT.
deterioration of the power-supply-rejection ratio (PSRR) at
total supply voltages below 8.3V. Operation at total supply
voltages below about 4.5V results in seriously degraded
performance.
Output Stage
The output stage consists of a drain-loaded inverting ampli-
fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer charac-
teristics of the output stage for a load returned to the nega-
tive supply rail are shown in Figure 2. Typical op amp loads
are readily driven by the output stage. Because large-signal
excursions are non-linear, requiring feedback for good wave-
form reproduction, transient delays may be encountered. As
a voltage follower, the amplifier can achieve 0.01% accuracy
levels, including the negative supply rail.
NOTE:
8. For general information on the characteristics of CMOS transis-
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
17.5
15
12.5
1kΩ
10
7.5
5
2.5
0
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
500Ω
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
A
= 25
o
C
LOAD RESISTANCE = 5kΩ
2kΩ
+
3
INPUT
2
A
V
≈
5X
A
V
≈
6000X
A
V
≈
30X
OUTPUT
6
V-
4
5
1
C
C
COMPENSATION
(WHEN REQUIRED)
8
STROBE
-
OFFSET
NULL
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with out-
put terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascade-connected load resistance provided by
PMOS transistors Q
3
and Q
5
. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
1
, diodes
D
1
through D
4
, and PMOS transistor Q
1
. A tap at the junction
of resistor R
1
and diode D
4
provides a gate-bias potential of
about 4.5V for PMOS transistors Q
4
and Q
5
with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
1
with respect to Terminal
7 to provide gate bias for PMOS transistors Q
2
and Q
3
. It
should be noted that Q
1
is “mirror-connected (see Note 8)” to
both Q
2
and Q
3
. Since transistors Q
1
, Q
2
, Q
3
are designed to
be identical, the approximately 200µA current in Q
1
estab-
lishes a similar current in Q
2
and Q
3
as constant current
sources for both the first and second amplifier stages, respec-
tively.
At total supply voltages somewhat less than 8.3V, zener
diode Z
1
becomes nonconductive and the potential,
developed across series-connected R
1
, D
1
-D
4
, and Q
1
, var-
ies directly with variations in supply voltage. Consequently,
the gate bias for Q
4
, Q
5
and Q
2
, Q
3
varies in accordance
with supply-voltage variations. This variation results in
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T
A
= 25
o
C when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T
A
= 25
o
C.
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the com-
mon-mode input voltage does not exceed 2V. As previously
noted, the input current is essentially the result of the leakage
current through the gate-protection diodes in the input circuit
and, therefore, a function of the applied voltage. Although the
finite resistance of the glass terminal-to-case insulator of the
国际半导体设备材料产业协会（SEMI）昨（10）日公布半导体设备资本支出的年中预测报告（SEMI Capital Equipment Forecast），预估2012年全球半导体设备营收规模将达到423.8亿美元，2013年将成长至467.1亿美元。
受惠平板电脑、智慧型手机与行动装置等消费性电子商品亮丽表现，半导体设备的采购需求仍将持续。SEMI在报告中指出，2011年半...[详细]
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
