ABRIDGED DATA SHEET
19-5931; Rev 0; 6/11
MAX24288
IEEE 1588 Packet Timestamper and Clock
and 1Gbps Parallel-to-Serial MII Converter
General Description
The MAX24288 is a flexible, low-cost IEEE 1588
clock and timestamper with an SGMII or 1000BASE-X
serial interface and a parallel MII interface that can
be configured for GMII, RGMII, or 10/100 MII. The
device provides all required hardware support for
high-accuracy time and frequency synchronization
using the IEEE1588 Precision Time Protocol. In both
the transmit and receive directions 1588 packets are
identified and timestamped with high precision.
System software makes use of these timestamps to
determine the time offset between the system and its
timing master. Software can then correct any time
error by steering the device’s 1588 clock subsystem
appropriately. The device provides the necessary I/O
to time-synchronize with a 1588 master elsewhere in
the same system or to be the master to which slave
components can synchronize.
In addition, the MAX24288 is a full-featured, gigabit
parallel-to-serial MII converter. It provides full SGMII
revision 1.8 compliance and also interfaces directly to
1Gbps 1000BASE-X SFP optical modules.
♦
♦
♦
♦
Highlighted Features
Complete Hardware Support for IEEE 1588
Ordinary, Boundary, and Transparent Clocks
Flexible Block for Any 1588 Architecture
1588 Clock Hardware
♦
Steerable by Software with 2
-8
ns Time
Resolution and 2
-32
ns Period Resolution
♦
1ns Input Timestamp Accuracy and Output
Edge Placement Accuracy
♦
Three Time/Frequency Controls: Direct Time
Write, Time Adjustment, and High-Resolution
Frequency Adjustment
♦
Programmable Clock and Time-Alignment I/O
♦
Input Event Timestamper Detects Incoming
Time Alignment (e.g., 1 PPS) or Clock Edges
♦
Output Event Generator Provides Output Clock
Signal or Time Alignment Signal
♦
Built-In Support for Telecom Equipment Timing
Architecture with Dual Redundant Timing Cards
1588 Timestamping Hardware
♦
1588 v1 and v2 Packets, Transmit and Receive
♦
Packet Classifier Supports 1588 Over Ethernet,
IPv4/UDP, IPv6/UDP, or MPLS and Is
Programmable for More Complex Stacks
♦
Supports 802.1Q VLAN Tags and MAC-in-MAC
♦
One-Step Operation: On-the-Fly Timestamp
Insertion or Transparent Clock Corrections; No
Need for Follow-Up Packets
♦
Can Insert All Timestamps, Receive
and
Transmit, Into Packets for Easy Software Access
♦
Optional Two-Step Operation
♦
Applications
1588-Enabled Equipment with 1G Ethernet Ports
Wireless Base Stations and Controllers
Switches, Routers, DSLAMs, PON Equipment
Pseudowire Circuit Emulation Equipment
Test and Measurement Systems
Industrial and Factory Automation Equipment
Medical Equipment
Parallel-to-Serial MII Conversion
♦
Bidirectional Wire-Speed Interface Conversion
PART
TEMP RANGE
PIN-PACKAGE
♦
Serial: 1000BASE-X or SGMII v1.8 (4, 6, or 8 Pin)
MAX24288ETK+
68 TQFN-EP*
-40°C to +85°C
♦
Parallel: GMII, RGMII,
or 10/100 MII
+Denotes
a lead(Pb)-free/RoHS-compliant package.
♦
Translates Link Speed and Duplex Mode
*EP = Exposed pad.
Negotiation Between MDIO and SGMII PCS
SPI is a trademark of Motorola, Inc.
♦
Full Support for 1588 + Synchronous Ethernet
♦
MDIO and SPI™ Interfaces
♦
1.2V Operation with 3.3V I/O
_________________________________________________________
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
♦
ABRIDGED DATA SHEET
Application Examples
Example 1: Single-Port 1588 Slave Node
Local
OSC
Ethernet
over fiber
Ethernet
over copper
MAX24288
SFP Module
-OR-
1.25G
Serial
-OR-
Processor
MAX24288
MDIO
1000BASE-T
PHY
SGMII
1588 recovered clock, e.g. 25MHz
1588 recovered time, e.g. 1 PPS
MAC
GMII
1588
Software
to frequency-syntonized
or time-synchronized
system components
Example 2: Multiport System with Switch-Connected 1588 Slave Node
SFP Modules
or
1000BASE-T
PHYs
1.25G
Serial
Ethernet
over fiber
GbE Switch
IC
SGMII
Local
OSC
Processor
to other PHYs
MDIO
MAC
MAX24288
GMII
1588
Software
1588 recovered clock, e.g. 25MHz
1588 recovered time, e.g. 1 PPS
to frequency-syntonized
or time-synchronized
system components
Example 3: Multiport System, Boundary or Transparent Clock, Port Card Logic
Ethernet
over fiber
Ethernet
over copper
SFP Module
-OR-
1.25G
Serial
-OR-
Processor
MAX24288
MDIO
1000BASE-T
PHY
MAC
GMII
1588
Software
packet data to/from central switch function
SGMII
system clock, e.g. 25MHz
system time, e.g. 1 PPS
line clock, e.g. 25MHz
line clocks from other ports
from central
timing function
to central timing function
for SyncE or
1588 + SyncE operation
Example 4: Multiport System, Boundary or Transparent Clock, Central Timing Function
Processor
1.25G
Serial
MAC
1588
Software
GMII
MDIO
MAX24288
1588 Clock
packet data to/from central switch function
Local OSC
Stratum 3+
from port cards,
for SyncE or
1588+SyncE operation
system time, e.g. 1 PPS
clk
to all port cards
system clock, e.g. 25MHz
other clocks,
various frequencies
line clocks, e.g. 25MHz
Clock Sync IC
DS31400
2
ABRIDGED DATA SHEET
Block Diagram
MAX24288
MAX24288
RXD[7:0]
RXCLK
RX_DV
RX_ER
COL
CRS
D
D
D
C
Rx SOP
Detect
1588
Packet
Classifier
and
Modifier
C
Rx SOP
RLB Loopback
Auto-
Negotiate
DLB Loopback
TLB Loopback
Receive
GMII
RGMII
MII
C
Rate
Adaption
Buffer
PCS
Decoder
(10b/8b)
RD[9:0]
125MHz
RCLK
RD
1.25GHz
Receive
CDR
RDP
RDN
De-
Serializer
TXD[7:0]
GTXCLK
TXCLK
TX_EN
TX_ER
Transmit
GMII
RGMII
MII
D
C
Rate
Adaption
Buffer
D
C
1588
Packet
Classifier
and
Modifier
TDP
D
C
PCS
Encoder
(8b/10b)
TD[9:0]
125MHz
TD
Serializer
625MHz
Transmit
Driver
TDN
TCLKP
TCLKN
Tx SOP
Detect
625MHz
125MHz, 62.5MHz, 25MHz, 2.5MHz
Tx SOP
MDIO
MDC
RST_N
CS_N
SCLK
SDI
SDO
ALOS
Tx SOP
Rx SOP
TX PLL
125MHz
REFCLK
125MHz, 8 phases
time
Control
and
Status
Time
Stamper
TS1
Time
Stamper
TS2
Time
Stamper
TS3
Prog. Event
Generator
PEG1
Prog. Event
Generator
PEG2
Output
Clock
Generator
1588
Time
Engine
JTRST_N
JTAG
GPIO Control
RCLK
Detailed Features
General Features
•
•
•
•
•
Control and status through MDIO interface or SPI interface
High-speed MDIO interface (12.5MHz slave only) with optional preamble suppression
Optional SPI 4-wire serial microprocessor interface (25MHz, slave only)
Operates from a 10, 12.8, 25, or 125MHz reference clock
Optional 125MHz output clock for MAC to use as GTXCLK
Parallel-Serial MII Conversion Features
•
•
•
•
•
•
•
•
•
Bidirectional wire-speed interface conversion
Serial Interface: 1000BASE-X or SGMII revision 1.8 (4, 6, or 8 Pins)
Parallel Interface:
GMII, RGMII (10, 100, and 1000Mbps) or
10/100 MII (DTE or DCE)
8-pin source-clocked SGMII mode
4-pin 1000BASE-X SerDes mode to interface with optical modules
Connects processors with parallel MII interfaces to 1000BASE-X SFP optical modules
Connects processors with parallel MII interfaces to PHY or switch ICs with SGMII interfaces
Interface conversion is transparent to MAC layer and higher layers
Translates link speed and duplex mode between GMII/MII MDIO and SGMII PCS
3
GPIO1
GPIO2
GPIO3
GPIO4
JTCLK
JTMS
JTDI
JTDO
GPIO5
GPIO6
GPIO7
GPO1
GPO2
ABRIDGED DATA SHEET
1588 Clock Features
•
•
•
•
•
Steerable by software with 2
-8
ns time resolution and 2
-32
ns period resolution
1ns input timestamp accuracy and output edge placement accuracy
Initialized and steered by software on an external processor to follow an external 1588 master
MAX24288
•
•
•
•
•
Three time/frequency controls: direct time write, time adjustment, and high-resolution frequency adjustment
Programmable clock and time-alignment I/O to synchronize all boards in large systems
o
Can frequency-lock to an input clock signal from elsewhere in the system
o
Can timestamp an input time alignment signal to time-lock to a master elsewhere in the system (e.g., 1 PPS)
o
Can provide an output clock signal to slave components elsewhere in the system
(125MHz/N , 1
≤
N
≤
255)
o
Can provide an output time alignment signal to slave components elsewhere in the system (e.g., 1 PPS)
Input signal timestamper can stamp rising edges, falling edges or both
Flexible programmable event generator (PEG) can output 1 PPS, one pulse per period, and a wide variety of
clock signals
Full support for dual redundant timing cards to match architecture used in SONET/SDH
Full support for switches and routers as transparent clocks or boundary clocks
Compatible with a wide variety of 1588 system architectures
1588 Timestamper Features
•
•
Identifies and timestamps 1588 v1 and v2 packets in both transmit and receive directions
Programmable packet classifier can identify packets transported by a variety of protocol stacks
o
1588 over Ethernet
o
1588 over IPv4/UDP
o
1588 over IPv6/UDP
o
1588 over MPLS
o
Configurable for more complex stacks as well
o
Recognizes 802.1Q VLAN tags and 802.1ah MAC-in-MAC
o
Can be configured to identify CESoP or SAToP for timing over adaptive-mode circuit emulation
Transmit and receive timestamping with 1ns resolution
One-step operation minimizes network bandwidth consumption
o
On-the-fly timestamp insertion
o
On-the-fly corrections in transparent clocks
o
No need for follow-up packets
Can insert ALL timestamps (receive
and
transmit) into packets for easy software access
o
Three insert methods: direct overwrite, read-add-write, and read-subtract-write
o
Eliminates reads from timestamp FIFOs
o
Minimizes processor bus traffic
Optional two-step operation
Optional 8-entry timestamp FIFOs
•
•
•
•
•
Synchronous Ethernet Features
•
•
•
Full support for 1588 over Synchronous Ethernet
Receive path bit clock can be output on a GPIO pin to line-time the system from the Ethernet port
Transmit path can be frequency-locked to a system clock signal connected to the REFCLK pin
Note to readers:
This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maxim-ic.com/MAX24288
and click on
Request Full Data Sheet.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0
2011 Maxim Integrated Products
4
Maxim is a registered trademark of Maxim Integrated Products.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
