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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11142-1E
MEMORY
4 M
×
64 BIT
SYNCHRONOUS DYNAMIC RAM DIMM
MB8504S064CA-102/-103/-102L/-103L
168-pin, 4 Clock, 1-bank, based on 4 M
×
16 Bit SDRAMs with SPD
s
DESCRIPTION
The Fujitsu MB8504S064CA is a fully decoded, CMOS Synchronous Dynamic Random Access Memory
(SDRAM) Module consisting of four MB81F641642C devices which organized as four banks of 4 M
×
16 bits and
a 2K-bit serial EEPROM on a 168-pin glass-epoxy substrate.
The MB8504S064CA features a fully synchronous operation referenced to a positive edge clock whereby all
operations are synchronized at a clock input which enables high performance and simple user interface
coexistence.
The MB8504S064CA is optimized for those applications requiring high speed, high performance and large
memory storage, and high density memory organizations.
This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface
is needed.
Un-buffered
s
PRODUCT LINE & FEATURES
Parameter
CL-t
RCD
-t
RP
Clock Frequency
Burst Mode Cycle Time
Output Valid from Clock
Two Banks Active
Power Dissipation
Self Refresh Mode
MB8504S064CA-102/-102L
2-2-2 clk min.
100 MHz max.
10 ns min.
6 ns max. (CL = 2)
2736 mW max.
14.4 mW max. (Std. power)
7.2 mW max. (Low power)
•
•
•
•
•
MB8504S064CA-103/-103L
3-2-2 clk min.
100 MHz max.
10 ns min.
6 ns max. (CL = 3)
2736 mW max.
14.4 mW max. (Std. power)
7.2 mW max. (Low power)
• Un-buffered 168-pin DIMM Socket Type
(Lead pitch: 1.27 mm)
• Conformed to JEDEC Standard (4 CLK)
• Organization: 4,194,304 words
×
64 bits
• Memory: MB81F641642C (4 M
×
16, 4-bank)
×
4 pcs
• 3.3 V
±0.3
V Supply Voltage
• All input/output LVTTL compatible
• Conformed to Intel PC/100 spec.
4096 Refresh Cycle every 65.6 ms
Auto and Self Refresh
CKE Power Down Mode
DQM Byte Masking (Read/Write)
Serial Presence Detect (SPD) with Serial EEPROM:
Intel SPD spec Rev 1.2A Format
• Module size:
1.375” (height)
×
5.25” (length)
×
0.157” (thickness)
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MB8504S064CA-102/-103/-102L/-103L
s
PACKAGE
168-pin plastic DIMM (socket type)
(MDS-168P-P40)
Package and Ordering Information
– 168-pin DIMM, order as MB8504S064CA-×××DG (DG = Std. power ver., Gold pad)
MB8504S064CA-×××LDG (LDG = Low power ver., Gold pad)
2
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MB8504S064CA-102/-103/-102L/-103L
s
PIN ASSIGNMENTS
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Signal
Name
V
SS
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
V
SS
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
V
CC
DQ
14
DQ
15
N.C.
N.C.
V
SS
N.C.
N.C.
V
CC
WE
DQMB
0
Pin
No.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Signal
Name
DQMB
1
CS
0
N.C.
V
SS
A
0
A
2
A
4
A
6
A
8
A
10
BA
1
V
CC
V
CC
CLK
0
V
SS
N.C.
CS
2
DQMB
2
DQMB
3
N.C.
V
CC
N.C.
N.C.
N.C.
N.C.
V
SS
DQ
16
DQ
17
Pin
No.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
Name
DQ
18
DQ
19
V
CC
DQ
20
N.C.
N.C.
N.C.
V
SS
DQ
21
DQ
22
DQ
23
V
SS
DQ
24
DQ
25
DQ
26
DQ
27
V
CC
DQ
28
DQ
29
DQ
30
DQ
31
V
SS
CLK
2
N.C.
N.C. (WP)
SDA
SCL
V
CC
Pin
No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Signal
Name
V
SS
DQ
32
DQ
33
DQ
34
DQ
35
V
CC
DQ
36
DQ
37
DQ
38
DQ
39
DQ
40
V
SS
DQ
41
DQ
42
DQ
43
Pin
No.
Signal
Name
Pin
No.
Signal
Name
113 DQMB
5
114 N.C.
115 RAS
116 V
SS
117 A
1
118 A
3
119 A
5
120 A
7
121 A
9
122 BA
0
123 A
11
124 V
CC
125 CLK
1
126 N.C.
127 V
SS
128 CKE
0
129 N.C.
130 DQMB
6
131 DQMB
7
132 N.C.
133 V
CC
134 N.C.
135 N.C.
136 N.C.
137 N.C.
138 V
SS
139 DQ
48
140 DQ
49
141 DQ
50
142 DQ
51
143 V
CC
144 DQ
52
145 N.C.
146 N.C.
147 N.C.
148 V
SS
149 DQ
53
150 DQ
54
151 DQ
55
152 V
SS
153 DQ
56
154 DQ
57
155 DQ
58
156 DQ
59
157 V
CC
158 DQ
60
159 DQ
61
160 DQ
62
161 DQ
63
162 V
SS
163 CLK
3
164 N.C.
165 SA
0
166 SA
1
167 SA
2
168 V
CC
100 DQ
44
101 DQ
45
102 V
CC
103 DQ
46
104 DQ
47
105 N.C.
106 N.C.
107 V
SS
108 N.C.
109 N.C.
110 V
CC
111 CAS
112 DQMB
4
3
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MB8504S064CA-102/-103/-102L/-103L
TOP VIEW
133.37 mm
D0
34.93 mm
D1
D3
D4
PLANE 0
1
10
11
40
41
84
85
94
95
124
125
PLANE 1
168
(MDS-168P-P40)
s
PIN DESCRIPTIONS
Symbol
A
0
to A
11
BA
0
, BA
1
RAS
CAS
WE
DQMB
0
to DQMB
7
CLK
0
to CLK
3
CKE
0
CS
0
, CS
2
I/O
I
I
I
I
I
I
I
I
I
Function
Address Input
Bank Select (Bank Address)
Row Address Strobe
Column Address Strobe
Write Enable
Data (DQ) Mask
Clock Input
Clock Enable
Chip Select
Symbol
DQ
0
to DQ
63
V
CC
V
SS
N.C.
SA
0
to SA
2
SCL
SDA
WP
I/O
—
—
—
I
I
I/O
—
Function
Power Supply (+3.3 V)
Ground (0 V)
No Connection
Serial PD Address Input
Serial PD Clock
Serial PD Address/Data
Input/Output
Serial PD Write Protect
—
I/O Data Input/Data Output
4
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MB8504S064CA-102/-103/-102L/-103L
s
SERIAL-PD INFORMATION
Byte
0
Function Described
Hex Value
-102/
-103/
102L
103L
80h
80h
08h
04h
0Ch
08h
01h
40h
00h
01h
A0h
60h
00h
80h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
14h
14h
32h
08h
20h
10h
20h
10h
00h
12h
04h
00h
00h
00h
00h
00h
00h
00h
64h
AFh
—
08h
04h
0Ch
08h
01h
40h
00h
01h
A0h
60h
00h
80h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
F0h
80h
00h
00h
14h
14h
14h
32h
08h
20h
10h
20h
10h
00h
12h
74h
00h
00h
00h
00h
00h
00h
00h
64h
ADh
—
128 Byte
Defines Number of Bytes Written into Serial Memory at Module
Manufacture
1
256 Byte
Total Number of Bytes of SPD Memory Device
2
SDRAM
Fundamental Memory Type
3
12
Number of Row Addresses
4
8
Number of Column Addresses
5
1 bank
Number of Module Banks
6
64 bit
Data Width
7
+0
Data Width (Continuation)
8
LVTTL
Interface Type
9
10/10 ns
SDRAM Cycle Time (Highest CAS Latency)
10
6/6 ns
SDRAM Access from Clock (Highest CAS Latency)
11
Non-Parity
DIMM Configuration Type
12
Self, Normal
Refresh Rate/Type
13
×16
Primary SDRAM Width
14
0
Error Checking SDRAM Width
15
1 Cycle
Minimum Clock Delay for Back to Back Random Column Addresses
16
1, 2, 4, 8, Page
Burst Lengths Supported
17
4 bank
Number of Banks on Each SDRAM Device
18
2, 3
CAS Latency Supported
19
0
CS Latency
20
0
Write Latency
21
UN-buffer
SDRAM Module Attributes
22
*1
SDRAM Device Attributes : General
23
10/15 ns
SDRAM Cycle Time (2nd. Highest CAS Latency)
24
6/8 ns
SDRAM Access from Clock (2nd. Highest CAS Latency)
25
No Support
SDRAM Cycle Time (3rd. Highest CAS Latency)
26
No Support
SDRAM Access from Clock (3rd. Highest CAS Latency)
27
20/20 ns
Minimum Row Precharge Time (t
RP
)
Row Activate to Row Activate Minimum (t
RRD
)
28
20/20 ns
RAS to CAS Delay Min. (t
RCD
)
29
20/20 ns
Minimum RAS Pulse Width
30
50/50 ns
Module Bank Density
31
32 MByte
Command and Address Signal Input Setup Time
32
2 ns
Command and Address Signal Input Hold Time
33
1 ns
Data Signal Input Setup Time
34
2 ns
Data Signal Input Hold Time
35
1 ns
36 to 61 Unused Storage Locations
—
SPD Data Revision Code
62
1.2
Checksum for Byte 0 to 62
63
*2
64 to 71 Manufacturer’s JEDEC ID Code Per JEP-108E
Optional
Manufacturing Location
72
Optional
73 to 90 Manufacturer’s Part Number
Optional
91 to 92 Revision Code
Optional
93 to 94 Manufacturing Data
Optional
95 to 98 Assembly Serial Number
Optional
99 to 125 Manufacturer Specific Data
Optional
Intel Specification Frequency
126
100 MHz
Intel Specification Details for 100 MHz Support
127
CL = 2, 3 / 3
Unused Storage Locations
128+
—
Note:
Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127.
Some or all data stored into Byte 0 to Byte 127 may be broken.
*1. Byte 22: SDRAM Device Attributes
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Supports
Supports
Supports
Lower V
CC
Upper V
CC
Write 1
Precharge
Auto-
TBD
TBD
tolerance
tolerance
/Read Burst
All
Precharge
0
0
0
0
1
1
1
*2. Byte 63: Checksum for Byte 0 to 62
This byte is the checksum for Byte 0 through 62. This byte contains the value of the low 8-bits of the
arithmetic sum of Byte 0 through 62.
5
Bit0
Supports
Early RAS
Precharge
0
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