HMCAD1051-40
v01.0411
Single 13/12-Bit 20/40 MSPS
A/D Converter
Features
• 13-Bit resolution
• 20/40 MsPs Maximum sampling rate
• Ultra-Low Power Dissipation: 19/33 mW
• 72 dB snr @ 8 MHz FIn
• Internal reference Circuitry
• 1.8 v Core supply voltage
• 1.7 - 3.6 v I/o supply voltage
• Parallel CMos output
• 6 x 6 mm 40-Pin QFn (LP6He) Package
general Description
the HMCAD1051-40 is a high performance ultra
low power analog-to-digital converter (ADC). the
ADC employs internal reference circuitry, a CMos
control interface, CMos output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
two idle modes with fast startup times exist. the
entire chip can either be put in standby Mode or
Power Down mode. the two modes are optimized
to allow the user to select the mode resulting in the
lowest possible energy consumption during idle
mode and startup.
the HMCAD1051-40 has a highly linear tHA optim-
ized for frequencies up to nyquist. the differential
clock interface is optimized for low jitter clock sources
and supports LvDs, LvPeCL, sine wave and CMos
clock inputs.
Pin compatible with HMCAD1041-40, HMCAD1041-80
and HMCAD1051-80.
0
A / D Converters - sMt
typical Applications
• Handheld Communication, PMr, sDr
• Medical Imaging
• Portable test equipment
• Digital oscilloscopes
• Baseband / IF Communication
• video Digitizing
• CCD Digitizing
Functional Diagram
Figure 1. Functional Block Diagram
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
0-1
HMCAD1051-40
v01.0411
Single 13/12-Bit 20/40 MSPS
A/D Converter
electrical Specifications
DC electrical Specifications
AvDD= 1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD= 2.5v, 20/40 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 13 bit output, unless
otherwise noted
Parameter
DC accuracy
no missing codes
offset error
Gain error
DnL
InL
v
CM
Analog Input
Input common mode
Full scale range, normal
Full scale range, option
Input capacitance
Bandwidth
Power Supply
Core supply voltage
I/o supply voltage
supply voltage to all 1.8v domain pins. see Pin Configura-
tion and Description
output driver supply voltage (ovDD). Must be higher than
or equal to Core supply voltage (v
ovDD
≥ v
DvDD
)
1.7
1.7
1.8
2.5
2
3.6
v
v
Analog input common mode voltage
Differential input voltage range,
Differential input voltage range, 1v (see section reference
voltages)
Differential input capacitance
Input Bandwidth
500
v
CM
-0.1
2
1
2
v
CM
+0.2
v
vpp
vpp
pF
MHz
Midscale offset
Full scale range deviation from typical
Differential nonlinearity (12-bit level)
Integral nonlinearity (12-bit level)
Common mode voltage output
± 0.2
± 0.6
v
AvDD
/2
Guaranteed
1
±6
LsB
%Fs
LsB
LsB
v
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
0-2
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1051-40
v01.0411
Single 13/12-Bit 20/40 MSPS
A/D Converter
AC electrical Specifications - 20 MSPS
AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Fs=20MsPs clock, 50% clock duty cycle, -1dBFs 8MHz input signal, 13 bit output, unless
otherwise noted.
Parameter
Performance
snr
signal to noise ratio
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 20 MHz
snDr
signal to noise and Distortion ratio
F
In
= 2 MHz
F
In
= 8 MHz
71
72.4
72
71.7
71.3
87
75
85
80
80
-90
-85
-95
-95
-95
-87
-75
-85
-80
-80
11.7
11.5
11.7
11.6
11.6
7.8
Digital core supply
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt enabled
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
Power Dissipation, sleep mode
20
3
1
1.7
1.3
14
5.1
19.1
9.9
9.2
dBFs
dBFs
dBFs
dBFs
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
mA
mA
mA
mA
mW
mW
mW
µW
mW
MsPs
MsPs
71.5
72.5
72.2
72.1
71.6
dBFs
dBFs
dBFs
dBFs
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
F
In
=~ Fs/2
F
In
= 20 MHz
sFDr
spurious Free Dynamic range
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 20 MHz
HD2
second order Harmonic Distortion
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 20 MHz
HD3
third order Harmonic Distortion
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 20 MHz
enoB
effective number of Bits
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 20 MHz
Power Supply
Analog supply current
Digital supply current
output driver supply
output driver supply
Analog power Dissipation
Digital power Dissipation
total power Dissipation
Power Down Dissipation
sleep Mode
Clock Inputs
Max. Conversion rate
Min. Conversion rate
0-3
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1051-40
v01.0411
Single 13/12-Bit 20/40 MSPS
A/D Converter
AC electrical Specifications - 40 MSPS
AvDD= 1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD= 2.5v, Fs= 40 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 13 bit output, unless
otherwise noted.
Parameter
Performance
snr
signal to noise ratio
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
snDr
signal to noise and Distortion ratio
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
sFDr
spurious Free Dynamic range
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
HD2
second order Harmonic Distortion
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
HD3
third order Harmonic Distortion
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
enoB
effective number of Bits
F
In
= 2 MHz
F
In
= 8 MHz
F
In
=~ Fs/2
F
In
= 30 MHz
Power Supply
Analog supply current
Digital supply current
output driver supply
output driver supply
Analog power Dissipation
Digital power Dissipation
total power Dissipation
Power Down Dissipation
sleep Mode
Clock Inputs
Max. Conversion rate
Min. Conversion rate
40
3
MsPs
MsPs
Power Dissipation, sleep mode
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
Digital core supply
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt enabled
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt disabled
13.4
1.7
3.3
2.4
24.1
9.1
33.2
9.7
14.2
mA
mA
mA
mA
mW
mW
mW
µW
mW
11.5
11.6
11.7
11.6
11.5
bits
bits
bits
bits
-75
-81
-81
-80
-80
dBc
dBc
dBc
dBc
-85
-90
-95
-95
-90
dBc
dBc
dBc
dBc
75
81
81
80
80
dBc
dBc
dBc
dBc
71
71.7
72.1
71.5
71.2
dBFs
dBFs
dBFs
dBFs
71.9
72.5
72.7
72
70.8
dBFs
dBFs
dBFs
dBFs
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
0-4
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1051-40
v01.0411
Single 13/12-Bit 20/40 MSPS
A/D Converter
Digital and timing Specifications
AvDD= 1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD= 2.5v, Conversion rate: Max specified, 50% clock duty cycle, -1 dBFs input signal, 5 pF capacitive
load on data outputs, unless otherwise noted
Parameter
Clock Inputs
Duty Cycle
Compliance
Input range
Input range
Input common mode voltage
Input capacitance
Timing
t
PD
t
sLP
t
ovr
t
AP
Єrms
t
LAt
t
D
t
DC
Logic Inputs
v
HI
v
HI
v
LI
v
LI
I
HI
I
LI
C
I
Logic Outputs
v
Ho
v
Lo
C
L
C
L
High Level output voltage
Low Level output voltage
Max capacitive load. Post-driver supply voltage equal to pre-
driver supply voltagev
ovDD
= v
oCvDD
Max capacitive load. Post-driver supply voltage above 2.25v
(1)
10
v
ovDD
-0.1
0.1
5
v
v
pF
pF
High Level Input voltage. v
ovDD
≥ 3.0v
High Level Input voltage. v
ovDD
= 1.7v – 3.0v
Low Level Input voltage. v
ovDD
≥ 3.0v
Low Level Input voltage. v
ovDD
= 1.7v – 3.0v
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
3
2
0.8 ·v
ovDD
0
0
0.8
0.2 ·v
ovDD
±10
±10
v
v
v
v
µA
µA
pF
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of ovDD
Differential
start up time from Power Down Mode to Active Mode
start up time from sleep Mode to Active Mode
out of range recovery time
Aperture Delay
Aperture jitter
Pipeline Delay
output delay (see timing diagram). 5pF load on output bits
output delay relative to CK_eXt (see timing diagram)
3
1
1
0.8
< 0.5
12
10
6
20
0.4
1.6
0.3
2
900
20
v
ovDD
-0.3
80
% high
vpp
vpp
v
pF
clock cycles
clock cycles
clock cycles
ns
ps
clock cycles
ns
ns
CMos, LvDs, LvPeCL, sine Wave
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
0-5
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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