HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
Features
•
10-bit resolution
•
65/80 MsPs maximum sampling rate
•
Ultra-Low Power Dissipation: 38/46 mW
•
61.6 dB snr @ 8 MHz FIn
•
Internal reference circuitry
•
1.8 v core supply voltage
•
1.7 - 3.6 v I/o supply voltage
•
Parallel CMos output
•
6 x 6 mm 40-Pin QFn (LP6He) Package
general Description
the HMCAD1041-80 is a high performance ultra
low power analog-to-digital converter (ADC). the
ADC employs internal reference circuitry, a CMos
control interface, CMos output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
two idle modes with fast startup times exist. the entire
chip can either be put in standby Mode or Power
Down mode. the two modes are optimized to allow
the user to select the mode resulting in the lowest
possible energy consumption during idle mode and
startup.
the HMCAD1041-80 has a highly linear tHA optim-
ized for frequencies up to nyquist. the differential
clock interface is optimized for low jitter clock sources
and supports LvDs, LvPeCL, sine wave and CMos
clock inputs.
Pin compatible with HMCAD1041-40, HMCAD1051-40
and HMCAD1051-80.
0
A / D Converters - sMt
typical Applications
•
Medical Imaging
•
Portable test equipment
•
Digital oscilloscopes
•
IF Communication
Functional Diagram
Figure 1.
Functional Block Diagram
0-1
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
electrical Specifications
DC electrical Specifications
AvDD= 1.8v, DvDD= 1.8v, DvDDCK= 1.8v, ovDD= 2.5v, 65/80 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, unless otherwise noted
Parameter
DC Accuracy
no missing codes
offset error
Gain error
DnL
InL
v
CM
Analog Input
Input common mode
Full scale range
Input capacitance
Bandwidth
Power Supply
Core supply voltage
I/o supply voltage
supply voltage to all 1.8v domain pins. see Pin Configuration and
Description
output driver supply voltage (ovDD). should be higher than or equal
to Core supply voltage (v
ovDD
≥ v
DvDD
)
1.7
1.7
1.8
2.5
2
3.6
v
v
Analog input common mode voltage
Differential input voltage range
Differential input capacitance
Input Bandwidth
500
v
CM
-0.1
2
2
v
CM
+0.2
v
vpp
pF
MHz
Midscale offset
Full scale range deviation from typical
Differential nonlinearity
Integral nonlinearity
Common mode voltage output
± 0.15
± 0.2
v
AvDD
/2
Guaranteed
1
±6
LsB
%Fs
LsB
LsB
v
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
0-2
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
AC electrical Specifications - 65 MSPS
AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Fs=65MsPs clock, 50% clock duty cycle, -1dBFs 8MHz input signal, unless otherwise noted.
Parameter
Performance
snr
signal to noise ratio
F
In
= 8 MHz
F
In
= 20 MHz
F
In
=~ Fs/2
F
In
= 40 MHz
snDr
signal to noise and Distortion ratio
F
In
= 8 MHz
F
In
= 20 MHz
60
61.6
61.6
60.4
61.1
70
77
77
70
75
-80
-90
-95
-85
-90
-70
-77
-77
-70
-75
9.7
9.9
9.9
9.7
9.9
13.8
Digital core supply
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt enabled
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
Power Dissipation, sleep mode
65
3
2.6
4.9
3.4
24.8
13.2
38
9.3
15.7
dBFs
dBFs
dBFs
dBFs
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
mA
mA
mA
mA
mW
mW
mW
µW
mW
MsPs
MsPs
60
61.6
61.6
61.5
61.3
dBFs
dBFs
dBFs
dBFs
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
F
In
=~ Fs/2
F
In
= 40 MHz
sFDr
spurious Free Dynamic range
F
In
= 8 MHz
F
In
= 20 MHz
F
In
=~ Fs/2
F
In
= 40 MHz
HD2
second order Harmonic Distortion
F
In
= 8 MHz
F
In
= 20 MHz
F
In
=~ Fs/2
F
In
= 40 MHz
HD3
third order Harmonic Distortion
F
In
= 8 MHz
F
In
= 20 MHz
F
In
=~ Fs/2
F
In
= 40 MHz
enoB
effective number of Bits
F
In
= 8 MHz
F
In
= 20 MHz
F
In
=~ Fs/2
F
In
= 40 MHz
Power Supply
Analog supply current
Digital supply current
output driver supply
output driver supply
Analog power Dissipation
Digital power Dissipation
total power Dissipation
Power Down Dissipation
sleep Mode
Clock Inputs
Max. Conversion rate
Min. Conversion rate
0-3
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
AC electrical Specifications - 80 MSPS
AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Fs=80MsPs clock, 50% clock duty cycle, -1dBFs 8MHz input signal, unless otherwise noted.
Parameter
Performance
snr
signal to noise ratio
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
snDr
signal to noise and Distortion ratio
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
sFDr
spurious Free Dynamic range
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
HD2
second order Harmonic Distortion
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
HD3
third order Harmonic Distortion
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
enoB
effective number of Bits
F
In
= 8 MHz
F
In
= 20 MHz
F
In
= 30 MHz
F
In
=~ Fs/2
Power Supply
Analog supply current
Digital supply current
output driver supply
output driver supply
Analog power Dissipation
Digital power Dissipation
total power Dissipation
Power Down Dissipation
sleep Mode
Clock Inputs
Max. Conversion rate
Min. Conversion rate
80
3
MsPs
MsPs
Power Dissipation, sleep mode
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
ovDD = 2.5v, 5pF load on output bits, F
In
= 1 MHz, CK_eXt disabled
Digital core supply
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt enabled
2.5v output driver supply, sine wave input, F
In
= 1 MHz, CK_eXt disabled
16.5
3.3
5.9
4.1
29.7
16.2
45.9
9.1
18.3
mA
mA
mA
mA
mW
mW
mW
µW
mW
9.7
9.9
9.8
9.8
9.5
bits
bits
bits
bits
-70
-75
-75
-75
-65
dBc
dBc
dBc
dBc
-80
-90
-95
-90
-80
dBc
dBc
dBc
dBc
70
75
75
75
65
dBc
dBc
dBc
dBc
60
61.3
60.7
61
59
dBFs
dBFs
dBFs
dBFs
60
61.6
61.2
61.3
61.3
dBFs
dBFs
dBFs
dBFs
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
0-4
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
HMCAD1041-80
v01.0411
Single 10-Bit 65/80 MSPS
A/D Converter
Digital and timing Specifications
AvDD=1.8v, DvDD=1.8v, DvDDCK=1.8v, ovDD=2.5v, Conversion rate: Max specified, 50% clock duty cycle, -1dBFs input signal, 5 pF capacitive
load on data outputs, unless otherwise noted
Parameter
Clock Inputs
Duty Cycle
Compliance
Input range
Input range
Input common mode
voltage
Input capacitance
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of ovDD
Differential
20
0.4
1.6
0.3
2
v
ovDD
-0.3
80
% high
vpp
vpp
v
pF
CMos, LvDs, LvPeCL, sine Wave
Condition
Min
Typ
Max
Unit
0
A / D Converters - sMt
Timing
t
PD
t
sLP
t
ovr
t
AP
Єrms
t
LAt
t
D
t
DC
Logic Inputs
v
HI
v
HI
v
LI
v
LI
I
HI
I
LI
C
I
Logic Outputs
v
Ho
v
Lo
C
L
C
L
High Level output voltage
Low Level output voltage
Max capacitive load. Post-driver supply voltage equal to pre-driver
supply voltage v
ovDD
= v
oCvDD
Max capacitive load. Post-driver supply voltage above 2.25v
(1)
10
v
ovDD
-0.1
0.1
5
v
v
pF
pF
High Level Input voltage. v
ovDD
≥ 3.0v
High Level Input voltage. v
ovDD
= 1.7v – 3.0v
Low Level Input voltage. v
ovDD
≥ 3.0v
Low Level Input voltage. v
ovDD
= 1.7v – 3.0v
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
3
2
0.8 ·v
ovDD
0
0
0.8
0.2 ·v
ovDD
±10
±10
v
v
v
v
µA
µA
pF
start up time from Power Down Mode to Active Mode
start up time from sleep Mode to Active Mode
out of range recovery time
Aperture Delay
Aperture jitter
Pipeline Delay
output delay (see timing diagram). 5pF load on output bits
output delay relative to CK_eXt (see timing diagram)
3
1
1
0.8
< 0.5
12
10
6
900
20
clock
cycles
clock
cylcles
clock
cycles
ns
ps
clock
cycles
ns
ns
(1) the outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible
to keep dynamic currents and resulting switching noise at a minimum
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
