DATASHEET
X9271
Single Supply/Low Power/256-Tap/SPI Bus Single, Digitally Controlled (XDCP™)
Potentiometer
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can
be directly written to and read by the user. The contents of
the WCR control the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8174
Rev 5.00
October 15, 2015
Features
• 256 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical at V
CC
= 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position on
Power-up
• Standby Current <3µA Max
• V
CC
= 2.7V to 5.5V Operation
• 50kΩ End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
V
CC
R
H
SPI
BUS
INTERFACE
ADDRESS
DATA
STATUS
WRITE
READ
TRANSFER
INC/DEC
BUS
INTERFACE
AND CONTROL
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
16 Bytes
50kΩ
256 TAPS
POT
V
SS
R
W
R
L
FN8174 Rev 5.00
October 15, 2015
Page 1 of 19
X9271
Ordering Information
PART NUMBER
(Notes
2, 3)
X9271UV14IZ (Note
1)
X9271UV14Z (Note
1)
X9271UV14IZ-2.7
X9271UV14IZ-2.7T1
X9271UV14Z-2.7
(No longer
available, recommended
replacement: X9271UV14IZ-2.7T1)
X9271UV14Z-2.7T1
(No longer
available, recommended
replacement: X9271UV14IZ-2.7T1)
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
X9271.
For more information on MSL please see Tech Brief
TB363.
PART
MARKING
X9271 UVZI
X9271 UVZ
X9271 UVZG
X9271 UVZG
X9271 UVZF
V
CC
LIMITS
(V)
5 ±10%
5 ±10%
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
POTENTIOMETER TEMP. RANGE
ORGANIZATION (kΩ)
(°C)
50
50
50
50
50
-40 to +85
0 to +70
-40 to +85
-40 to +85
0 to +70
PACKAGE
Pb-Free
PKG.
DWG. #
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
X9271 UVZF
2.7 to 5.5
50
0 to +70
14 Ld TSSOP (4.4mm) M14.173
Pin Configuration
X9271
14 LD TSSOP
TOP VIEW
S0
A0
NC
CS
SCK
SI
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
HOLD
A1
WP
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN NAME
SO
A0
NC
CS
SCK
SI
V
SS
WP
A1
HOLD
R
W
R
H
R
L
V
CC
Serial Data Output
Device Address
No Connect
Chip Select
Serial Clock
Serial Data Input
System Ground
Hardware Write Protect
Device Address
Device Select. Pause the serial bus.
Wiper Terminal of Potentiometer
High Terminal of Potentiometer
Low Terminal of Potentiometer
System Supply Voltage
FUNCTION
FN8174 Rev 5.00
October 15, 2015
Page 2 of 19
X9271
Detailed Functional Diagram
V
CC
Bank 0
R
0
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
D ATA
R
2
R
3
R
1
Power-on Recall
Wiper
Counter
Register
(WCR)
50kΩ
256 Taps
R
H
R
L
R
W
Bank 1
R
0
R
1
Bank 2
R
0
R
1
Bank 3
R
0
R
1
Control
R
2
R
3
R
2
R
3
R
2
R
3
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
V
SS
Circuit-Level Applications
• Vary the gain of a voltage amplifier.
• Provide programmable DC reference voltages for
comparators and detectors.
• Control the volume in audio circuits.
• Trim out the offset voltage error in a voltage amplifier circuit.
• Set the output voltage of a voltage regulator.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and
Q-factor in filter circuits.
• Set the scale factor and zero point in sensor signal
conditioning circuits.
• Vary the frequency and duty cycle of timer ICs.
• Vary the DC biasing of a pin diode attenuator in RF circuits.
• Provide a control variable (I, V, or R) in feedback
circuits.
System-Level Applications
• Adjust the contrast in LCD displays.
• Control the power level of LED transmitters in
communication systems.
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems.
• Control the gain in audio and home entertainment systems.
• Provide the variable DC bias for tuners in RF
wireless systems.
• Set the operating points in temperature control
systems.
• Control the operating point for sensors in industrial systems.
• Trim offset and gain errors in artificial intelligence
systems.
FN8174 Rev 5.00
October 15, 2015
Page 3 of 19
X9271
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
The Serial Output (SO) is the serial data output pin. During a
read cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
SERIAL INPUT (SI)
The Serial Input (SI) is the serial data input pin. All operational
codes, byte addresses, and data to be written to the
potentiometers and potentiometer registers are input on this
pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The Serial Clock (SCK) input is used to clock data into and out
of the X9271.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is under
way, HOLD may be used to pause the serial communication with
the controller without resetting the serial sequence. To pause,
HOLD must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW. If
the pause feature is not used, HOLD should be held HIGH at all
times. CMOS level input.
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set the 8-bit
slave address. A match in the slave address serial data stream
must be made with the address input in order to initiate
communication with the X9271.
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is deselected, the
SO pin is at high impedance and (unless an internal write cycle
is under way) the device is in standby state. CS LOW enables
the X9271, placing it in the active power mode. It should be
noted that after a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Other Pins
HARDWARE WRITE PROTECT INPUT (WP)
The Hardware Write Protect Input (WP) pin, when LOW,
prevents nonvolatile writes to the data registers.
NO CONNECT
No Connect pins should be left floating. These pins are used
for Intersil manufacturing and testing purposes.
Principles of Operation
Device Description
SERIAL INTERFACE
The X9271 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in on
the rising SCK. CS must be LOW and the HOLD and WP pins
must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three-state outputs. This can help to reduce system pin
count.
ARRAY DESCRIPTION
The X9271 is composed of a resistor array (Figure
1).
The
array contains the equivalent of 255 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor segment
is a CMOS switch connected to the wiper (R
W
) output. Within
each individual array, only one switch may be turned on at a
time.
These switches are controlled by a Wiper Counter Register
(WCR). The eight bits of the WCR (WCR[7:0]) are decoded to
select, and enable, one of 256 switches (Table
1).
POWER-UP AND POWER-DOWN RECOMMENDATIONS
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins, provided that V
CC
is always more positive
than or equal to V
H
, V
L
, and V
W
; i.e., V
CC
V
H
, V
L
, V
W
. The
V
CC
ramp rate specification is always in effect.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal connections
on a mechanical potentiometer.
R
W
The wiper pin (R
W
) is equivalent to the wiper terminal of a
mechanical potentiometer.
Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY GROUND
(V
SS
)
The System Supply Voltage (V
CC
) pin is the system supply
voltage. The Supply Ground (V
SS
) pin is the system ground.
FN8174 Rev 5.00
October 15, 2015
Page 4 of 19
X9271
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
SERIAL
BUS
INPUT
REGISTER 0
(DR0)
8
BANK_0 Only
R
H
C
O
U
N
T
E
R
D
E
C
O
D
E
REGISTER 1
(DR1)
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
REGISTER 2
(DR2)
REGISTER 3
(DR3)
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
R
L
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Device Description
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register (WCR) for the
DCP potentiometer. The WCR can be envisioned as an 8-bit
parallel and serial load counter, with its outputs decoded to
select one of 256 switches along its resistor array (Table
1).
The contents of the WCR can be altered in four ways:
1. It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
2. It can be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register instruction (parallel load).
3. It can be modified one step at a time by the Increment/
Decrement instruction.
4. It is loaded with the contents of its Data Register zero (DR0)
upon power-up.
The WCR is a volatile register; that is, its contents are lost
when the X9271 is powered down. Although the register is
automatically loaded with the value in DR0 upon power-up, this
may be different from the value present at power-down. Power-
up guidelines are recommended to ensure proper loading of
the R0 value into the WCR. The DR0 value of Bank 0 is the
default value.
Registers and the associated WCR. All operations changing
data in one of the Data Registers are nonvolatile operations
and take a maximum of 10ms.
If the application does not require storage of multiple settings
for the potentiometer, the Data Registers can be used as
regular memory locations for system parameters or user
preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~255).
Status Register (SR)
The 1-bit Status Register is used to store the system status
(Table
3).
WIP: Write In Progress status bit; read only.
• WIP = 1 indicates that a high-voltage write cycle is in
progress.
• WIP = 0 indicates that no high-voltage write cycle is in
progress
.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]:
Used to store current wiper position (Volatile, V)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
V
(MSB)
V
V
V
V
V
V
V
(LSB)
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host (Table
2).
Data can also be transferred between any of the four Data
FN8174 Rev 5.00
October 15, 2015
Page 5 of 19
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
