®
X9119
Single Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
July 9, 2008
FN8162.4
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9119 integrates a single digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP™ can be used as a three-terminal potentiometer
or as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 40Ω Typical @ V
CC
= 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 3µA Max
• V
CC
: 2.7V to 5.5V Operation
• 100kΩ End-to-End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9118
• Pb-Free available (RoHS compliant)
Functional Diagram
V
CC
R
H
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
CONTROL
V
SS
NC
NC
R
W
R
L
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
X9119
Ordering Information
PART NUMBER
X9119TV14I
X9119TV14IZ (Note)
X9119TV14
X9119TV14Z (Note)
X9119TV14-2.7*
X9119TV14Z-2.7* (Note)
X9119TV14I-2.7
X9119TV14IZ-2.7* (Note)
PART
MARKING
X9119 TVI
X9119 TVZI
X9119 TV
X9119 TVZ
X9119 TVF
X9119 TVZF
X9119 TVG
X9119 TVZG
2.7 to 5.5
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(kΩ)
100
TEMP
RANGE
(°C)
PKG. DWG.#
PACKAGE
M14.173
-40 to +85 14 Ld TSSOP (4.4mm)
-40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
0 to +70
0 to +70
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
M14.173
-40 to +85 14 Ld TSSOP (4.4mm)
-40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Detailed Functional Diagram
V
CC
POWER ON
RECALL
SCL
SDA
A2
A1
A0
WP
DR0
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
DR2
CONTROL
R
W
DR3
DR1
R
H
100KΩ
1024-TAPS
R
L
WIPER
COUNTER
REGISTER
(WCR)
V
SS
2
FN8162.4
July 9, 2008
X9119
Applications
Circuit Level
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Pin Assignments
PIN
NUMBER
1, 3, 10
2
4
5
6
7
8
9
11
12
13
14
PIN NAME
NC
A0
A2
SCL
SDA
V
SS
WP
A1
R
W
R
H
R
L
V
CC
No Connect
Device Address for 2-wire bus
Device Address for 2-wire bus
Serial Clock for 2-wire bus
Serial Data Input/Output for 2-wire bus
System Ground
Hardware Write Protect
Device Address for 2-wire bus
Wiper terminal of the Potentiometer
High terminal of the Potentiometer
Low terminal of the Potentiometer
System Supply Voltage
FUNCTION
System Level
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from an 2-wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
SERIAL CLOCK (SCL)
This input is used by 2-wire master to supply 2-wire serial
clock to the X9119.
DEVICE ADDRESS (A
2
–A
0
)
Pinout
X9119
(14 LD TSSOP)
TOP VIEW
NC
A0
NC
A2
SCL
SDA
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
NC
A1
WP
The Address inputs are used to set the least significant 3 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9119. A maximum
of 8 devices may occupy the 2-wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
3
FN8162.4
July 9, 2008
X9119
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of 1024
switches.
The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9119 will be
considered a slave device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Figure 3).
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9119 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (Figure 3).
Principals of Operation
The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters and
the serial interface logic providing direct communication
between the host and the digitally controlled potentiometer.
This section provides detail description of the following:
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Resistor Array Description
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments that are
connected in series (Figure 1). The physical ends of each
array are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
inputs).
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
SERIAL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
RH
10
10
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
IF WCR = 000[HEX] THEN R
W
= R
L
IF WCR = 3FF[HEX] THEN R
W
= R
H
RL
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION
4
FN8162.4
July 9, 2008
X9119
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 3).
ACKNOWLEDGE
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9119 will
respond with a final acknowledge (see Figure 2).
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ST AR T
ACKNO WLEDGE
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9119 initiates the internal write cycle. ACK polling,
Flow 1, can be initiated immediately. This involves issuing
the start condition followed by the device slave address. If
the X9119 is still busy with the write operation, no ACK will
be returned. If the X9119 has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.
FLOW 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
5
FN8162.4
July 9, 2008
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
