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LTC2656CIUFD-L16PBF

产品描述Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference
文件大小2MB,共26页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
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LTC2656CIUFD-L16PBF概述

Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

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LTC2656
Octal 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
FEATURES
Precision 10ppm/°C Max Reference
n
Maximum INL Error: ±4LSB at 16 Bits
n
Guaranteed Monotonic over Temperature
n
Selectable Internal or External Reference
n
2.7V to 5.5V Supply Range (LTC2656-L)
n
Integrated Reference Buffers
n
Ultralow Crosstalk Between DACs(<1nV•s)
n
Power-On-Reset to Zero-Scale/Mid-scale
n
Asynchronous LDAC Update Pin
n
Tiny 20-Lead 4mm × 5mm QFN and 20-Lead
Thermally Enhanced TSSOP Packages
n
DESCRIPTION
The LTC
®
2656 is a family of octal 16-/12-bit rail-to-rail
DACs with a precision integrated reference. The DACs have
built-in high performance, rail-to-rail, output buffers and
are guaranteed monotonic. The LTC2656-L has a full-scale
output of 2.5V with the integrated 10ppm/°C reference and
operates from a single 2.7V to 5.5V supply. The LTC2656-H
has a full-scale output of 4.096V with the integrated refer-
ence and operates from a 4.5V to 5.5V supply. Each DAC can
also operate with an external reference, which sets the DAC
full-scale output to two times the external reference voltage.
These DACs communicate via a SPI/MICROWIRE™ com-
patible 4-wire serial interface which operates at clock rates
up to 50MHz. The LTC2656 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
tied to V
CC
, the DACs reset to mid-scale.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 6891433.
APPLICATIONS
n
n
n
n
n
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
Automotive
BLOCK DIAGRAM
REFCOMP
GND
REGISTER
REGISTER
REGISTER
REGISTER
REFLO
V
OUTA
DAC A
REF
REF
INTERNAL REFERENCE
REF
V
CC
DAC H
REF
V
OUTH
4
3
DAC G
REF
V
OUTG
INL (LSB)
2
1
0
–1
–2
–3
–4
128
DAC E
POWER-ON RESET
CONTROL LOGIC
SCK
LDAC
32-BIT SHIFT REGISTER
DECODE
V
OUTE
PORSEL
SDO
SDI
CLR
2656 TA01a
REFIN/OUT
INL vs Code
REGISTER
REGISTER
REGISTER
V
OUTB
DAC B
REF
REGISTER
REGISTER
REGISTER
V
OUTC
DAC C
REF
REGISTER
REGISTER
DAC F
REF
V
OUTF
DAC A
DAC B
DAC C
DAC D
16384
32768
CODE
49152
DAC E
DAC F
DAC G
DAC H
65535
2656 TA01b
REGISTER
REGISTER
REGISTER
V
OUTD
DAC D
CS/LD
REGISTER
2656fa
1

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