Datasheet
Standard EEPROMs
Plug & Play EEPROMs
(for Display)
BU9882xx-W Series (1K×2BANK)
●General
Description
BU9882F-W,BU9882FV-W are dual port EEPROMs compatible with the DDC2
TM
. 2 independent ports allow 2 EDID
channels to be read simultaneously.
●Features
Designed for use with DDC2
TM
2-port simultaneous read function
Operating voltage range: 2.5V-5.5V
Page write function: 8bytes
Low power consumption
Active (at 5V)
: 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
Data security
Write protection with WP
Write protection at low power supply voltage
Initial data=FFh
Data retention: 10years
Rewriting possible up to 100,000 times
●BU9882xx-W
series
Capacity
Type
2Kbit
BU9882
●Packages
W(Typ.) x D(Typ.) x H(Max.)
SOP14
8.70mm x 6.20mm x 1.71mm
SSOP-B14
5.00mm x 6.40mm x 1.35mm
Power source Voltage
2.5V to 5.5V
SOP14
●
SSOP-B14
●
●Absolute
Maximum Ratings
Parameter
Symbol
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature
Terminal Voltage
*1 6.8V (Max.)
Ratings
-0.3 to +6.5
0.45 (SOP14)
0.35 (SSOP-B14)
-65 to +125
-40 to +85
-0.3 to Vcc+1.0
*1
Unit
V
W
℃
℃
V
Remarks
Reduce by 4.5 mW/C over 25C.
Reduce by 3.5 mW/C over 25C
V
CC
Pd
Tstg
Topr
‐
●Memory
cell characteristics
Parameter
Write/Erase Cycle
Data Retention
Min.
100,000
10
Limits
Typ.
－
－
Max
－
－
Unit
Times
Years
○Product
structure：Silicon monolithic integrated circuit
.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This
product is not designed protection against radioactive rays
1/18
TSZ02201-0R2R0G100300-1-2
21.Aug.2015 Rev.002
BU9882xx-W Series
(1K×2BANK)
●Recommended
Operating Ratings
Parameter
Symbol
Supply Voltage
V
CC
Input voltage
VIN
Ratings
2.5 to 5.5
0 to Vcc+1.0
Unit
V
●Electrical
characteristics
- DC (Unless otherwise specified, Ta=-40℃ to +85℃½V
CC
=2.5V to 5.5V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
“H” Input Voltage 1
VIH1
2.0
-
-
V
V
CC
≧4.0V
“L” Input Voltage 1
VIL1
-
-
0.8
V
“L” Input Voltage 2
VIL2
-
-
0.2V
CC
V
V
CC
＜4.0V
SDA_PC0/1, IOL=3.0mA *１
“L” output Voltage
VOL1
-
-
0.4
V
SCL_PC0/1,DDCENA, BANKSEL,
Input Leakage Current 1
ILI1
-1
-
1
µA
VIN=0V to V
CC
+1.0
Input Leakage Current 2
Output Leakage Current
Operating Current
Standby Current
ILI2
ILO
ICC
ISB
-1
-1
-
-
-
-
1.5
0.1
50
1
3.0
5
µA
µA
mA
µA
WP
SDA_PC0/1,SCL/SDA_MON(DDCENA=GND),
VOUT=0V to V
CC
+1.0
fSCL=400kHz, V
CC
=5.5V
tWR=10ms
SCL/SDA_PC0/1=V
CC
SCL/SDA_MON=H-Z
DDCENA=WP=BANKSEL=GND
DUALPCB=V
CC
*1 IOL at monitor mode (DDCENA＝HIGH) is the sum of current flowing from the pull up resistor at the SDA_MON side to the pull up resistance
at SDA_PC0/PC1
- AC (Unless otherwise specified, Ta=-40℃ to +85℃,V
CC
=2.5V to 5.5V)
Fast-mode
V
CC
=2.5V to 5.5V
Parameter
Symbol
Min.
Typ.
Max.
Clock Frequency
fSCL
-
-
400
Data Clock High Period
tHIGH
0.6
-
-
Data Clock Low Period
tLOW
1.3
-
-
SDA and SCL Rise Time
tR
-
-
0.3
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time(SCL)
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tSU:STO
tBUF
tWR
tI
-
0.6
0.6
0
100
-
0.6
1.3
-
-
-
-
-
-
-
-
-
-
-
-
0.3
-
-
-
-
0.9
-
-
10
0.1
Standard-mode
V
CC
=2.5V to 5.5V
Min.
Typ.
Max.
-
-
100
4.0
-
-
4.7
-
-
-
-
1.0
-
4.0
4.7
0
250
-
4.0
4.7
-
-
-
-
-
-
-
-
-
-
-
-
0.3
-
-
-
-
3.5
-
-
10
0.1
Unit
Typ.
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
ms
µs
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/18
TSZ02201-0R2R0G100300-1-2
21.Aug.2015 Rev.002
BU9882xx-W Series
●Block
Diagram
(1K×2BANK)
WP
N.C.
N.C.
●Pin
Configuration
(TOP VIEW)
V
CC
WP
DUALPCB BANKSEL
DDCENA SCL_MON SDA_MON
BU9882F - W
BU9882FV -W
SCL_PC0 SDA_PC0
N.C.
SCL_PC1 SDA_PC1
N.C.
GND
●Pin
Descriptions
Pin Name
V
CC
GND
N.C.
SCL_PC0
SDA_PC0
SCL_PC1
SDA_PC1
SCL_MON
SDA_MON
DDCENA
BANKSEL
DUALPCB
WP
I/O
-
-
-
IN
IN/OUT
IN
IN/OUT
OUT
OUT
IN
IN
IN
IN
Power Supply
Ground (0V)
No Connection
Serial Clock Input, Access to BANK0 at DUAL PORT mode
Access to BANK0 or to BANK1 at SINGLE PORT mode
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK0 at DUAL PORT mode, Access to BANK0 or to BANK1 at SINGLE PORT mode
Functions
Serial Clock Input
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
Serial Clock Output
Connected to SCL_PC0/1 at DDCENA="High", "Hi-Z" output at DDCENA="Low"
Slave and Word Address Serial Data Output
Connected to SCL_PC0/1 DDCENA="High", "Hi-Z" output at DDCENA="Low"
Control of SCL_MON, SDA_MON
Select a SCL/SDA_MON Connected Port at DUAL PORT mode
Selected a BANK at SINGLE PORT mode
Control of DUAL PORT/SINGLE PORT mode
Write Protect Control
An open drain output requires a pull-up resistor.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/18
TSZ02201-0R2R0G100300-1-2
21.Aug.2015 Rev.002
BU9882xx-W Series
●Synchronous
data timing
(1K×2BANK)
t
R
SCL
t
F
t
HIGH
SCL
t
HD
:STA
SDA
(IN)
t
BUF
SDA
(OUT)
t
PD
t
SU
:DAT
t
LOW
t
HD
:DAT
t
SU
:STA
SDA
t
HD
:STA
t
SU
:STO
START BIT
STOP BIT
Figure 1. Synchronous Data Timing
・SDA
data is latched into the chip at the rising edge of the SCL clock.
・The
output date toggles at the falling edge of the SCL clock.
●Write
cycle timing
SCL
SDA
D0
WRITE DATA (n)
ACK
t
WR
STOP CONDITION
START CONDITION
Figure 2. Write Cycle Timing
●Operation
notes
○DDCENA
Operation
When DDCENA is set to High, SCL_PC0/1 and SDA_PC0/1 will be connected to SCL_MON and SDA_MON, respectively.
Therefore, monitoring of the communications between the PC and EEPROM, and the communications of the MONITOR
and PC, is possible.
Selection of PC0/PC1 is determined according to the state of the DUALPCB and BANKSEL inputs.
When DDCENA is Low, the SCL/SDA_MON output is set to "Hi-Z".
SCL_MON,SDA_MON
DUALPCB
BANKSEL
(CONNECTION PORT)
Low
PC0 PORT
Low (DUAL PORT)
High
PC1 PORT
Low
High (SINGLE PORT)
PC0 PORT
High
○BANKSEL
BANKSEL serves as an input for connection port of SCL/SDA_MON during DUAL PORT mode.
It turns into the BANK selection terminal of internal memory in SINGLE PORT mode.
Only the PC0 port can access the memory in SINGLE PORT mode.
DUALPCB
Low (DUAL PORT)
High (SINGL PORT)
BANKSEL
Low
High
Low
High
CONNECTION BANK
PC0 PORT：BANK0
PC1 PORT：BANK1
BANK0
BANK1
○WP
When WP=Low, all data at all addresses are write-protected. The terminal has a built-in pull down resister. Make sure
that WP=High when writing data.
Utilize this function in order to prevent incorrect write command input from the PC, as well as incorrect input during
communication between the PC and monitor.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/18
TSZ02201-0R2R0G100300-1-2
21.Aug.2015 Rev.002
BU9882xx-W Series
(1K×2BANK)
○Data
Read
The data read function allows simultaneous read from SCL_PC0/1, SDA_PC0/1 in DUAL PORT mode.
○Data
Write
Write operation is performed using either PC0/1 (SCL or SDA) even when accessed simultaneously in DUAL PORT mode.
Port selection is made by detecting the data D0 of the first byte of the WRITE command input.
After this, the other port is made unavailable for both READ and WRITE commands until the write operation is completed.
S
T
A
R
T
SDA_PC
W
R
I
T
E
WA
6
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
WA
0
A
C
K
DATA
1 0 1 0 0 0
0
R A
/ C
W K
*
D7
D0
A
C
K
*:Don’t care
D0 detected first write operation
performed through the port
During other port is write command.
this ack is no output.
Figure 3. Write Cycle Timing
○START
Condition
All commands are preceeded by the START condition, which is a High to Low transition of SDA when SCL is High. This
IC continuously monitors the SDA and SCL lines for the START condition and will not respond to any commands until this
condition has been met.
○STOP
Condition
All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is HIGH.
(See Figure 1.)
○WRITE
Command
Unless a STOP condition is executed, the data will not be written into the memory array.
○DEVICE
ADDRESSING
Following a START condition, the Master outputs the device address of the slave to be accessed.
The most significant four bits of the Slave address are the "device type indentifier".
For the IC this is fixed as "1010".
The next three bits are "000".
The last bit of the stream determines the operation to be performed.
When set to "1", Read operation is selected ; when set to "0", Write operation is selected.
R/W set to "0"
・ ・ ・ ・ ・ ・ ・ ・
WRITE
R/W set to "1"
・ ・ ・ ・ ・ ・ ・ ・
READ
1010
0
0
0
R/W
―
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/18
TSZ02201-0R2R0G100300-1-2
21.Aug.2015 Rev.002
Linux开发
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
