V916764B24QA
64M x 64 HIGH PERFORMANCE
UNBUFFERED DDR2 SDRAM SODIMM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
200-pin, unbuffered small outline, dual in-line
memory module(SODIMM)
JEDEC standard 1.8V + 0.1V power supply
VDDQ=1.8V + 0.1V
Fast data transfer rate: PC2-3200, PC2-4200, or
PC2-5300
Programmable CAS Latency(CL): 3, 4, 5
Programmable Additive Latency(AL): 0, 1, 2, 3
and 4
Write Latency(WL)=Read Latency(RL)-1
Programmble burst lengths: 4 or 8
Differential data strobe (DQS, DQS#)
(Single ended data strobe option)
On-die termination (ODT)
Adjustable data-output drive strength
64ms, 8192-cycle refresh
Serial Presence Detect (SPD) with EEPROM
Description
The V916764B24QA memory module is orga-
nized as 67,108,864 x 64 bits in a 200 pin memory
module. The 64M x 64 memory module uses 8 Pro-
MOS 32M x 16 DDR2 SDRAMs. The x64 modules
are ideal for use in high performance computer sys-
tems where increased memory density and fast
access times are required.
Speed Grade
DDR2-400
PC2-3200 (D3)
Bandwith@CL=3
Bandwith@CL=4
Bandwith@CL=5
CL-tRCD-tRP
400
400
400
3-3-3
DDR2-533
PC2-4200 (E4)
400
533
533
4-4-4
DDR2-667
PC2-5300 (F5)
400
533
667
5-5-5
Units
Mbps
Mbps
Mbps
tCK
V916764B24QA Rev 1.3 March 2007
1
ProMOS TECHNOLOGIES
Pin Description
Symbol
CK0-CK2
CK0#-CK2#
CKE0-CKE1
Input
Type
Input
Function
V916764B24QA
CK and CK# are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing
of positive edge of CK and negative edge of CK#. Output (read) data is reference to the crossing of
CK and CK# (Both directions of crossing)
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivat-
ing the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disbled, new command are ignored but previous opera-
tions continue. This signal provides for external rank selection on systems with multiple ranks
RAS#, CAS#, WE# (ALONG WITH CS#) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ# and DM pins, assuming the function is
enabled in the Extended Mode Register Set (EMRS).
Reference voltage for SSTL 18 inputs.
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all cur-
rent DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If
AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction
with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident
with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
V
DD
/V
DDQ
planes on these modules.
Data strobe for input and output data. its edge-aligned with read data, center aligned with write data.
DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.
These signals and tied at the system planar to either V
SS
or V
DD
to configure the serial SPD EER-
POM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDD to act as a pullup on the system board.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pullup onthe system board.
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DDQ
power plane.
EEPROM supply is operable from 1.7V to 3.6V.
S0#- S1#
RAS#, CAS#, WE#
ODT0-ODT1
V
REF
V
DDQ
BA0-BA1
Input
Input
Input
Supply
Supply
Input
A0-A13
Input
DQ0-DQ63
CB0-CB7
DM0-DM8
In/Out
Input
V
DD
,V
SS
DQS0-DQS8
DQS0#-DQS8#
SA0-SA2
SDA
SCL
V
DD
SPD
Supply
In/Out
Input
In/Out
Input
Supply
V916764B24QA Rev 1.3 March 2007
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
