JANSR2N7292
Formerly FRF150R4
June 1998
25A, 100V, 0.070 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Intersil Corporation has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Chan-
nel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hard-
ness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to exhibit mini-
mal characteristic changes to total dose (GAMMA) and
neutron (n
o
) exposures. Design and processing efforts are
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
Also available at other radiation and screening levels. See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional informa-
tion.
[ /Title
(JANS
R2N72
92)
/Sub-
ject
(25A,
100V,
0.070
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
MOS-
FET)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
ductor,
25A,
100V,
0.070
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
Features
• 25A, 100V, r
DS(ON)
= 0.070Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 7.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cm
2
Ordering Information
PART NUMBER
JANSR2N7292
PACKAGE
TO-254AA
BRAND
JANSR2N7292
Symbol
D
Die family TA17651.
MIL-PRF-19500/605.
G
S
Package
TO-254AA
G
S
D
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
©2001 Fairchild Semiconductor Corporation
JANSR2N7292 Rev. A
JANSR2N7292
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JANSR2N7292
100
100
25
20
75
±20
125
50
1.00
75
25
75
-55 to 150
300
9.3
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
JC
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
100
-
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 50V,
I
D
= 25A
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
5.0
4.0
-
25
250
100
200
1.84
0.070
0.140
134
628
642
490
552
314
17
46
164
1.0
48
UNITS
V
V
V
V
µA
µA
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
R
θ
JC
R
θ
JA
V
DS
= 80V,
V
GS
= 0V
V
GS
=
±20V
V
GS
= 10V, I
D
= 25A
I
D
= 20A,
V
GS
= 10V
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on slash sheet)
Gate Charge at 10V
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Gate Charge Drain
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
V
DD
= 50V, I
D
= 25A,
R
L
= 2.0Ω, V
GS
= 10V,
R
GS
= 25Ω
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 25A
I
SD
= 25A, dI
SD
/dt = 100A/µs
MIN
0.6
-
TYP
-
-
MAX
1.8
1400
UNITS
V
ns
©2001 Fairchild Semiconductor Corporation
JANSR2N7292 Rev. A
JANSR2N7292
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 10V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 80V
V
GS
= 10V, I
D
= 25A
V
GS
= 10V, I
D
= 20A
MIN
100
2.0
-
-
-
-
MAX
-
4.0
100
25
1.84
0.070
UNITS
V
V
nA
µA
V
Ω
Typical Performance Curves
40
Unless Otherwise Specified
100
30
I
D
, DRAIN (A)
I
D
, DRAIN CURRENT (A)
T
C
= 25
o
C
100ms
1ms
10ms
10
20
10
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100ms
0
-50
0
50
100
150
0.1
100
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
10
THERMAL RESPONSE (Z
θ
JC
)
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
t
1
t
2
NORMALIZED
0.01
10
0
10
1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
©2001 Fairchild Semiconductor Corporation
JANSR2N7292 Rev. A
JANSR2N7292
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
V
DD
t
ON
t
d(ON)
t
OFF
t
d(OFF)
t
r
t
f
90%
R
L
V
DS
V
GS
= 10V
DUT
0V
R
GS
V
DS
90%
10%
10%
90%
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
10V
Q
G
Q
GS
V
G
Q
GD
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
JANSR2N7292 Rev. A
JANSR2N7292
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS)
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
SYMBOL
I
GSS
I
DSS
r
DS(ON)
V
GS(TH)
TEST CONDITIONS
V
GS
=
±20V
V
DS
= 80% Rated Value
T
C
= 25
o
C at Rated I
D
I
D
= 1.0mA
MAX
±20
(Note 4)
±25
(Note 4)
±20%
(Note 5)
±20%
(Note 5)
UNITS
nA
µA
Ω
V
Screening Information
TEST
Gate Stress
Pind
Pre Burn-In Tests (Note 6)
Steady State Gate Bias (Gate Stress)
V
GS
= 30V, t = 250µs
Required
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25
o
C)
MIL-STD-750, Method 1042, Condition B
V
GS
= 80% of Rated Value, T
A
= 150
o
C, Time = 48 hours
All Delta Parameters Listed in the Delta Tests and Limits Table
MIL-STD-750, Method 1042, Condition A
V
DS
= 80% of Rated Value, T
A
= 150
o
C, Time = 240 hours
5%
MIL-S-19500, Group A,
Subgroups 2 and 3
JANS
Interim Electrical Tests (Note 6)
Steady State Reverse Bias (Drain Stress)
PDA
Final Electrical Tests (Note 6)
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
Unclamped Inductive Switching
Thermal Response
Thermal Impedance
SYMBOL
SOA
I
AS
∆V
SD
∆V
SD
TEST CONDITIONS
V
DS
= 80V, t = 10ms
V
GS(PEAK)
= 15V, L = 0.1mH
t
H
= 100ms; V
H
= 25V; I
H
= 4A
t
H
= 500ms; V
H
= 25V; I
H
= 4A
MAX
5
75
136
187
UNITS
A
A
mV
mV
©2001 Fairchild Semiconductor Corporation
JANSR2N7292 Rev. A
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