HI-1565, HI-1566
July 2009
MIL-STD-1553 / 1760
5V Monolithic Dual Transceivers
PIN CONFIGURATIONS
44 N/C
43 BUSA
42 BUSA
41 BUSA
40 BUSA
39 VDDA
38 VDDA
37 TXA
36 TXA
35 N/C
34 N/C
N/C 1
RXENA 2
GNDA 3
GNDA 4
GNDA 5
VDDB 6
VDDB 7
BUSB 8
BUSB 9
BUSB 10
BUSB 11
DESCRIPTION
The HI-1565 and HI-1566 are low power CMOS dual
transceivers designed to meet the requirements of the
MIL-STD-1553 /1760 specifications.
The transmitter section of each bus takes complementary
CMOS / TTL Manchester II bi-phase data and converts it to
differential voltages suitable for driving the bus isolation
transformer. Separate transmitter inhibit control signals
are provided for each transmitter.
The receiver section of each bus converts the 1553 bus bi-
phase differential data to complementary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic 0 (HI-1565) or
logic 1 (HI-1566).
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer.
1565PCI
1565PCT
1566PCI
1566PCT
33 N/C
32 N/C
31 TXINHA
30 RXA
29 RXA
28 N/C
27 N/C
26 TXB
25 TXB
24 TXINHB
23 N/C
44 Pin Plastic 7mm x 7mm
Chip-scale package
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
20
19
18
17
16
15
14
13
12
11
TXA
TXA
TXINHA
RXA
RXA
TXB
TXB
TXINHB
RXB
RXB
FEATURES
!
Compliant to MIL-STD-1553A & B,
MIL-STD-1760, ARINC 708A
!
CMOS technology for low standby power
!
Smallest footprint available in 44-pin plastic
chip-scale package with integral heatsink
20 Pin Plastic ESOIC - WB package
N/C 12
N/C 13
N/C 14
N/C 15
RXENB 16
GNDB 17
GNDB 18
GNDB 19
RXB 20
RXB 21
N/C 22
1565PSI
1565PST
1565PSM
1566PSI
1566PST
1566PSM
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
20 TXA
19 TXA
!
Less than 1.0W maximum power dissipation
!
BUS pins ESD protected to greater than 8KV
!
Also available in DIP and small outline
(ESOIC) package options
1565CDI
1565CDT
1565CDM
1566CDI
1566CDT
1566CDM
18 TXINHA
17 RXA
16 RXA
15 TXB
14 TXB
13 TXINHB
12 RXB
11 RXB
!
Industrial and extended temperature ranges
!
Industry standard pin configurations
(DS1565 Rev. F)
20 Pin Ceramic DIP package
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/09
HI-1565, HI-1566
PIN DESCRIPTIONS
PIN
(DIP/ESOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
RXB
RXB
TXINHB
TXB
TXB
RXA
RXA
TXINHA
TXA
TXA
FUNCTION
power supply
analog output
analog output
digital input
power supply
power supply
analog output
analog output
digital input
power supply
digital output
digital output
digital input
digital input
digital input
digital output
digital output
digital input
digital input
digital input
+5 volt power for bus A
DESCRIPTION
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1565) or High (HI-1566)
Ground for bus A
+5 volt power for bus B
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and RXB low (HI-1565) or High (HI-1566)
Ground for bus B
Receiver B output, inverted
Receiver B output, non-inverted
Transmit inhibit, bus B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
Receiver A output, non-inverted
Transmit inhibit, bus A. If high BUSA, BUSA disabled
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1565 family of data bus transceivers contain differ-
ential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
TRANSMITTER
Data input to the device’s transmitter section is from the
complementary CMOS /TTL inputs TXA/B and TXA/B.
The transmitter accepts Manchester II bi-phase data and
converts it to differential voltages on BUSA/B and BUSA/B.
The transceiver outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling
methods produce a nominal voltage on the bus of 7.5 volts
peak to peak.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are ei-
ther at a logic “1” or logic “0” simultaneously. A logic “1” ap-
plied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
TXA/B.
RECEIVER
The receiver accepts bi-phase differential data from the
MIL-STD-1553 bus through the same direct or transformer
coupled interface as the transmitter. The receiver’s differ-
ential input stage drives a filter and threshold comparator
that produces CMOS/TTL data at the RXA/B and RXA/B
output pins.
Each set of receiver outputs can be independently forced
to a logic "0" (HI-1565) or logic “1” (HI-1566) by setting
RXENA or RXENB low.
MIL-STD-1553 BUS INTERFACE
A direct coupled interface (see Figure 2) uses a 1:2.5 ratio
isolation transformer and two 55 ohm isolation resistors
between the transformer and the bus.
In a transformer coupled interface (see Figure 3), the
transceiver is connected to a 1:1.79 isolation transformer
which in turn is connected to a 1:1.4 coupling transformer.
The transformer coupled method also requires two
coupling resistors equal to 75% of the bus characteristic
impedence (Zo) between the coupling transformer and the
bus.
HOLT INTEGRATED CIRCUITS
2
HI-1565, HI-1566
Each Bus
TRANSMITTER
Data Bus
Isolation
Transformer
Coupler
Network
Direct
or
Transformer
BUSA/B
TXA/B
Transmit
Logic
TXA/B
TXINHA/B
RECEIVER
RXA/B
Receive
Logic
RXA/B
RXENA/B
BUSA/B
Slope
Control
Input
Filter
Comparator
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
Vin
(Line to Line)
t
DR
t
DR
t
DR
t
DR
RXA/B
t
RG
t
RG
RXA/B
HOLT INTEGRATED CIRCUITS
3
HI-1565, HI-1566
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Logic input voltage range
Receiver differential voltage
Driver peak output current
Power dissipation at 25°C
ceramic DIL, derate
Solder Temperature
Junction Temperature
Storage Temperature
-0.3 V to +7 V
-0.3 V dc to +5.5 V
10 Vp-p
Temperature Range
+1.0 A
1.0 W
7mW/°C
275°C for 10 sec.
175°C
-65°C to +150°C
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
VDD....................................... 5V... ±5%
DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, GND = 0V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
Total Supply Current
SYMBOL
VDD
ICC1
ICC2
ICC3
CONDITION
Not Transmitting
Transmit one bus @
50% duty cycle
Transmit one bus @
100% duty cycle
Not Transmitting
Transmit one bus @
100% duty cycle
Digital inputs
Digital inputs
V
IH
= 4.9V, Digital inputs
V
IL
= 0.1V, Digital inputs
I
OUT
= -0.4mA, Digital outputs
I
OUT
= 4.0mA, Digital outputs
MIN
4.75
TYP
5
14
200
400
MAX
5.25
22
340
550
0.11
UNITS
V
mA
mA
mA
W
W
V
Power Dissipation
PD1
PD2
0.70
2.0
1.4
1.4
0.95
Min. Input Voltage
Max. Input Voltage
Min. Input Current
Max. Input Current
Min. Output Voltage
Max. Output Voltage
RECEIVER
Input resistance
Input capacitance
(HI)
(LO)
(HI)
(LO)
(HI)
(LO)
V
IH
V
IL
I
IH
I
IL
V
OH
V
IH
0.8
20
V
µA
µA
V
-20
2.7
0.4
V
(Measured at Point “A
D
“ in Figure 2 unless otherwise specified)
R
IN
C
IN
CMRR
V
IN
V
ICM
Detect
No Detect
V
THD
V
THND
V
THD
V
THND
1 Mhz Sine Wave
(Measured at Point “A
D
“ in Figure 2)
1 MHz Sine Wave
(Measured at Point “A
T
“ in Figure 3)
Differential
-5.0
1.15
Differential
Differential
40
9
5.0
20.0
0.28
0.86
14.0
0.20
20
5
Kohm
pF
dB
Vp-p
V-pk
Vp-p
Vp-p
Vp-p
Vp-p
Common mode rejection ratio
Input Level
Input common mode voltage
Threshold Voltage - Direct-coupled
Threshold Voltage - Transformer-coupled Detect
No Detect
HOLT INTEGRATED CIRCUITS
4
HI-1565, HI-1566
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 5.0V, GND = 0V, T
A
= Operating Temperature Range (unless otherwise specified).
PARAMETER
TRANSMITTER
Output Voltage
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
(Measured at Point “A
D
” in Figure 2 unless otherwise specified)
Direct coupled
Transformer coupled
V
OUT
V
OUT
V
ON
Direct coupled
V
DYN
V
DYN
R
OUT
C
OUT
35 ohm load
(Measured at Point “A
D
“ in Figure 2)
70 ohm load
(Measured at Point “A
T
“ in Figure 3)
Differential, inhibited
35 ohm load
(Measured at Point “A
D
“ in Figure 2)
70 ohm load
(Measured at Point “A
T
“ in Figure 3)
Differential, not transmitting
1 MHz sine wave
-90
-250
10
15
7.0
20.0
9.0
27.0
10.0
90
250
Vp-p
Vp-p
mVp-p
mV
mV
Kohm
pF
Output Noise
Output Dynamic Offset Voltage
Transformer coupled
Output resistance
Output Capacitance
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, GND = 0V, T
A
=Operating Temperature Range (unless otherwise specified).
PARAMETER
RECEIVER
Receiver Delay
Receiver gap time
Receiver Enable Delay
TRANSMITTER
Driver Delay
Rise time
Fall Time
Inhibit Delay
SYMBOL
tDR
tRG
tREN
TEST CONDITIONS
From input zero crossing to RXA/B or RXA/B
Spacing between RXA/B and RXA/B pulses
From RXENA/B rising or falling edge to
RXA/B or RXA/B
MIN
TYP
MAX
450
UNITS
ns
ns
ns
(Measured at Point “A
D
” in Figure 2)
90
365
40
(Measured at Point “A
D
” in Figure 2)
tDT
tr
tf
tDI-H
tDI-L
TXA/B, TXA/B to BUSA/B, BUSA/B
35 ohm load
35 ohm load
Inhibited output
Active output
100
100
150
300
300
100
150
ns
ns
ns
ns
ns
TRANSMITTER
TXA/B
TXA/B
TXINHA/B
BUSA/B
1:2.5
55
W
35
W
Point “A
D
“
BUSA/B
Isolation
Transformer
55
W
55
W
Point “A
D
“
35
W
55
W
2.5:1
RECEIVER
RXA/B
RXA/B
Isolation
Transformer
RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
