TS27L2C,I,M
PRECISION VERY LOW POWER
CMOS DUAL OPERATIONAL AMPLIFIERS
s
VERY LOW POWER CONSUMPTION :
10µA/op
s
OUTPUT VOLTAGE CAN SWING TO
GROUND
s
EXCELLENT PHASE MARGIN ON
CAPACITIVE LOADS
s
STABLE AND LOW OFFSET VOLTAGE
s
THREE INPUT OFFSET VOLTAGE
SELECTIONS
DESCRIPTION
These devices are low cost, low power dual oper-
ational amplifiers designed to operate with single
or dual supplies. These operational amplifiers use
the ST silicon gate CMOS process allowing an ex-
cellent consumption-speed ratio. These series are
ideally suited for low consumption applications.
Three power consumptions are available allowing
to have always the best consumption-speed ratio:
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
P
TSSOP8
(Thin Shrink Small Outline Package)
u
I
CC
= 10µA/amp.: TS27L2 (very low power)
u
I
CC
= 150µA/amp.: TS27M2 (low power)
u
I
CC
= 1mA/amp.: TS272 (standard)
These CMOS amplifiers offer very high input im-
pedance and extremely low input currents. The
major advantage versus JFET devices is the very
low input currents drift with temperature (see fig-
ure 2).
ORDER CODE
Package
Part Number
Temperature Range
N
TS27L2C/AC/BC
0°C, +70°C
TS27L2I/AI/BI
-40°C, +125°C
TS27L2M/AM/BM
-55°C, +125°C
Example :
TS27L2ACN
•
•
•
D
•
•
•
P
•
•
•
PIN CONNECTIONS
(top view)
1
2
3
4
-
+
-
+
8
7
6
5
N =
Dual in Line Package (DIP)
D =
Small Outline Package (SO) - also available in Tape & Reel (DT)
P =
Thin Shrink Small Outline Package (TSSOP) - only available
in Tape & Reel (PT)
1 - Output 1
2 - Inverting Input 1
3 - Non-inverting Input 1
4 - V
CC
-
5 - Non-inverting Input 2
6 - Inverting Input 2
7 - Output 2
8 - V
CC
+
November 2001
1/9
TS27L2C,I,M
BLOCK DIAGRAM
V
CC
Current
source
xI
Input
differential
Second
stage
Output
stage
Output
V
CC
E
E
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC+
V
id
V
i
I
o
I
in
T
oper
T
stg
Parameter
Supply Voltage
1)
Differential Input Voltage
2)
Input Voltage
3)
Output Current for V
CC+
≥
15V
Input Current
Operating Free-Air Temperature Range
Storage Temperature Range
0 to +70
TS27L2C/AC/BC
TS27L2I/AI/BI
18
±18
-0.3 to 18
±30
±5
-40 to +125
-65 to +150
-55 to +125
TS27L2M/AM/BM
Unit
V
V
V
mA
mA
°C
°C
1. All values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive supply voltage.
OPERATING CONDITIONS
Symbol
V
CC+
V
icm
Supply Voltage
Common Mode Input Voltage Range
Parameter
Value
3 to 16
0 to V
CC+
- 1.5
Unit
V
V
2/9
V
CC
T
24
T
25
T
26
T
6
T
8
T
28
T
1
T
11
Input
R1
C1
Input
T
27
T
5
T
10
T
15
SCHEMATIC DIAGRAM
(for 1/2 TS27L2)
R
2
T
2
T
12
T
17
T
18
T
7
T
3
Output
T
19
T
4
T
23
T
16
T
9
T
13
T
14
T
20
T
22
T
29
T
21
V
CC
TS27L2C,I,M
3/9
TS27L2C,I,M
ELECTRICAL CHARACTERISTICS
V
CC
+
= +10V, V
CC
-
= 0V, T
amb
= +25°C (unless otherwise specified)
TS27L2C/AC/BC
Symbol
Parameter
Min.
Input Offset Voltage
V
O
= 1.4V, V
ic
= 0V
V
io
T
min
≤
T
amb
≤
T
max
TS27L2C/I/M
TS27L2AC/AI/AM
TS27L2B/C/I/M
TS27L2C/I/M
TS27L2AC/AI/AM
TS27L2B/C/I/M
Typ.
1.1
0.9
0.25
Max.
10
5
2
12
6.5
3
TS27L2I/AI/BI
TS27L2M/AM/BM
Min.
Typ.
Max.
10
5
2
12
6.5
3.5
Unit
1.1
0.9
0.25
mV
DV
io
I
io
Input Offset Voltage Drift
Input Offset Current note
1)
V
ic
= 5V, V
O
= 5V
T
min
≤
T
amb
≤
T
max
Input Bias Current - see note 1
V
ic
= 5V, V
O
= 5V
T
min
≤
T
amb
≤
T
max
High Level Output Voltage
V
id
= 100mV, R
L
= 1MΩ
T
min
≤
T
amb
≤
T
max
Low Level Output Voltage
V
id
= -100mV
Large Signal Voltage Gain
V
iC
= 5V, R
L
= 1MΩ, V
o
= 1V to 6V
T
min
≤
T
amb
≤
T
max
Gain Bandwidth Product
A
v
= 40dB, R
L
= 1MΩ, C
L
= 100pF, f
in
= 100kHz
Common Mode Rejection Ratio
V
iC
= 1V to 7.4V, V
o
= 1.4V
Supply Voltage Rejection Ratio
V
CC+
= 5V to 10V, V
o
= 1.4V
Supply Current (per amplifier)
A
v
= 1, no load, V
o
= 5V
T
min
≤
T
amb
≤
T
max
Output Short Circuit Current
V
o
= 0V, V
id
= 100mV
Output Sink Current
V
o
= V
CC
, V
id
= -100mV
Slew Rate at Unity Gain
R
L
= 1MΩ, C
L
= 100pF, V
i
= 3 to 7V
Phase Margin at Unity Gain
A
v
= 40dB, R
L
= 1MΩ, C
L
= 100pF
Overshoot Factor
Equivalent Input Noise Voltage
f = 1kHz, R
s
= 100Ω
Channel Separation
65
60
60
45
8.8
8.7
2
1
100
1
150
9
8.8
8.6
50
100
60
40
2
1
200
1
300
9
µV/°C
pA
I
ib
pA
V
OH
V
OL
A
vd
V
50
100
mV
V/mV
GBP
CMR
SVR
0.1
80
80
10
15
17
65
60
0.1
80
80
10
15
18
MHz
dB
dB
I
CC
I
o
I
sink
SR
φm
K
OV
e
n
V
o1
/V
o2
1.
µA
60
45
0.04
45
30
68
120
60
45
0.04
45
30
68
120
mA
mA
V/µs
Degrees
%
nV
-----------
-
Hz
dB
Maximum values including unavoidable inaccuracies of the industrial test.
4/9
TS27L2C,I,M
TYPICAL CHARACTERISTICS
Figure 1 :
Supply Current (each amplifier) versus
Supply Voltage
20
Figure 3b :
High Level Output Voltage versus
High Level Output Current
20
OUTPUT VOLTAGE, V
OH
(V)
SUPPLY CURRENT, I
CC
(
µ
A)
15
T
amb
= 25
°
C
A
V
= 1
V
O
= V
CC
/ 2
T
amb
= 25° C
16
12
8
4
0
-50
V
id
= 100mV
V
CC
= 16V
10
V
CC
= 10V
5
0
4
8
12
16
SUPPLY VOLTAGE, V
CC
(V)
-40
-30
-20
-10
OUTPUT CURRENT, I
OH
(mA)
0
Figure 2 :
Input Bias Current versus Free Air
Temperature
100
Figure 4a :
Low Level Output Voltage versus Low
Level Output Current
1 .0
O U T P U T V O L T A G E , V
O L
(V )
INPUT BIAS CURRENT, IIB (pA)
V
CC
= 10V
V
i
= 5V
0 .8
0 .6
0 .4
0 .2
V
CC
= 3V
V
CC
= 5V
10
T amb = 2 5 °C
V ic = 0 .5 V
V id = -1 0 0 m V
1
2
3
1
25
50
100
TEMPERATURE, T
amb
(°C)
75
125
0
O U T P U T C U R R E N T , I
O L
(m A )
Figure 3a :
High Level Output Voltage versus
High Level Output Current
5
Figure 4b :
Low Level Output Voltage versus Low
Level Output Current
3
O U T P U T V O L T A G E , V OL (V )
OUTPUT VOLTAGE, V
OH
(V)
4
3
2
1
0
-10
T
amb
= 25° C
V
id
= 100mV
V
CC
= 5V
V
C C
= 10V
2
V
C C
= 1 6 V
1
T amb = 2 5 °C
V i = 0 .5 V
Vid = -1 0 0 m V
V
CC
= 3V
-8
-6
-4
-2
0
0
4
8
12
16
20
OUTPUT CURRENT, I
OH
(mA)
O U T P U T C U R R E N T , I OL (m A )
5/9
FPGA/CPLD
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