HI-5000, HI-5001, HI-5002
September 2011
1Mbps CAN Transceiver with
Low Power Standby Mode
PIN CONFIGURATIONS
(Top Views)
TXD - 1
GND - 2
VDD - 3
RXD - 4
HI-5000PSI
8 - STB
7 - CANH
6 - CANL
5 - SPLIT
GENERAL DESCRIPTION
The HI-5000 is a 1 Mbps Controller Area Network (CAN)
transceiver. It interfaces between a CAN protocol con-
troller and the physical wires of the bus in a CAN network.
Differential output amplitude and current drive capability
are specifically enhanced to meet the needs of long cable
runs typical in many applications such as industrial auto-
mation.
The HI-5000 supports two modes of operation: Normal
Mode and Standby Mode. The Standby Mode is a very
low-current mode which continues to monitor bus activity
and allows an external controller to manage wake-up.
Superior common-mode receiver performance makes
the device especially suitable for applications where
ground reference voltages may vary from point to point
over long distances along the CAN bus. In addition, the
HI-5000 provides a SPLIT pin to give an output reference
voltage of VDD/2 which can be used for stabilizing the re-
cessive bus level when the split termination technique is
used to terminate the bus.
A TXD dominant time-out feature also protects the bus
from being driven into a permanent dominant state (so-
called “babbling idiot”) if pin TXD becomes permanently
low due to application failure.
The device also has short circuit protection to +/-58V on
CANH, CANL and SPLIT pins and ESD protection to
+/- 6kV on all pins.
The HI-5001 is identical to the HI-5000 except the SPLIT
pin is substituted with a VIO supply voltage pin. This al-
lows the HI-5001 to interface directly with controllers with
2.5V or 3.3V supply voltages.
The HI-5002 provides both the SPLIT and VIO supply
voltage pins in a compact 16-pin QFN.
All three devices are available in industrial -40 C to +85 C
temperature ranges. “RoHS compliant” lead-free options
are also available.
o
o
TXD - 1
GND - 2
VDD - 3
RXD - 4
HI-5001PSI
8 - STB
7 - CANH
6 - CANL
5 - VIO
8 - PIN PLASTIC NARROW BODY SOIC
16
15
14
13
12
11
10
9
-
TXD
-
STDBY
GND
GND
VDD
VDD
1
2
3
4
HI-5002PCI
CANH
CANH
CANL
CANL
16 - PIN PLASTIC 4 x 4mm QFN
FEATURES
·
Compatible with ISO 11898-5 standard.
·
Signaling rates up to 1Mbit/s.
·
Internal VDD/2 voltage source available to stabilize the
·
·
·
·
·
recessive bus level if split termination is used (HI-5000
SPLIT pin).
VIO input on HI-5001 allows for direct interfacing with 2.5V
or 3.3V controllers.
Detection of permanent dominant on TXD pin (babbling
idiot protection).
High impedance allows connection of up to 120 nodes.
CANH, CANL and SPLIT pins short-circuit proof to +/-58V.
Will not disturb the bus if unpowered.
( DS 5000 Rev. B)
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www.holtic.com
VIO
RXD
-
SPLIT
5
6
7
8
09/11
HI-5000, HI-5001, HI-5002
PIN DESCRIPTIONS
SIGNAL
TXD
GND
VDD
RXD
CANL
CANH
STB
SPLIT
(HI-5000)
VIO
(HI-5001)
FUNCTION
INPUT
POWER
POWER
OUTPUT
BUS I/O
BUS I/O
INPUT
INPUT
INPUT
DESCRIPTION
100kOhm internal pull-up. Transmit Data Input.
Chip 0V supply
Positive supply, 5V +/-5%. Bypass with 0.1uF ceramic capacitor.
Receive Data Output.
CAN Bus Line Low.
CAN Bus Line High.
100kOhm internal pull-up. Standby Mode selection input. Drive STB low or connect to GND
for Normal operation. Drive STB high to select low-current Standby Mode.
Supplies a VDD/2 output to provide recessive bus level stabilization when a split termination
is used to terminate the bus.
Connect to a 2.5V or 3.3V supply to allow compatibility of all digital I/O (RXD, TXD, STB)
with a low voltage controller input.
BLOCK DIAGRAM
VDD
V Split
SPLIT
(HI-5000)
CANH
TXD
Dominant
Detect
CANL
Driver
TXD
Standby
Control
STB
VIO
(HI-5001)
RXD
MUX
Main
Receiver
GND
Low power
Standby Rx
Figure 1. HI-5000 Functional Block Diagram
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HI-5000, HI-5001, HI-5002
FUNCTIONAL DESCRIPTION
OPERATING MODES
The HI-5000 provides two modes of operation which are
selectable via the STB pin. Table 1 summarizes the modes.
Table 1 - Operating Modes
due to an unpowered node with high leakage from the bus
lines to ground), the split circuit will force the recessive
voltage to VDD/2.
INTERNAL PROTECTION FEATURES
Short-circuit protection
Short-circuit protection is provided on the CANH, CANL and
SPLIT pins. These pins are protected from ESD to over 6KV
(HBM) and from shorts between -58V and +58V continuous,
as specified in ISO 11898-5. The short circuit current is limited
to less than 200mA typical.
TXD permanent dominant time-out
Normal Mode
Normal mode is selected by setting the STB pin to a LOW
logic level (GND). In this mode, the transceiver transmits and
receives data in the usual way from the CANH and CANL bus
lines. The differential receiver converts the analog bus data
to digital data which is output on the RXD pin (Note: the RXD
output on HI-5001 is compatible with 2.5V or 3.3V controllers
if the VIO pin is connected to a 2.5V or 3.3V supply).
Standby Mode
Standby Mode is selected by setting the STB pin to a HIGH
logic level. In this mode, the transmitter is switched off and a
low power differential receiver monitors the bus lines for
activity. A dominant signal of more than 3
m
s will be reflected
on the RXD pin as a logic LOW, where it may be detected by
the host as a wake-up request. The device will not leave
standby mode until the host forces the STB pin to a logic low.
A timer circuit prevents the bus lines being driven into a
permanent dominant state, which would result in a situation
blocking all bus traffic. This could happen in the case of the
TXD pin becoming permanently low due to a hardware or
application failure. The timer is triggered by a negative edge
on the TXD pin (start of dominant state). If the TXD pin is not
set high (recessive state) after a typical time of 2ms, the
transmitter outputs will be disabled, putting the bus lines into
the recessive state. The timer is reset by a positive edge on
the TXD pin. Note that the minimum TXD dominant time-out
time, tdom = 300μs, defines the minimum possible bit rate of
40kbit/s (the CAN protocol specifies a maximum of 11
successive dominant bits − 5 successive dominant bits
immediately followed by an error frame).
Fail-safe features
Pin TXD has a pull up in order to set a recessive level if pin
TXD is left open.
Pins TXD and STB will become floating if power is lost. This
will prevent reverse currents via these pins.
MODE
Normal
Standby
STB pin
LOW
HIGH
SPLIT Circuit
The SPLIT pin provides a stable VDD/2 DC voltage. This
pin can be used to stabilize the recessive common mode
voltage by connecting the SPLIT pin to the center tap of the
split termination (see figure 7). In the case of a recessive
bus voltage dropping below the ideal value of VDD/2 (e.g.
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HI-5000, HI-5001, HI-5002
TIMING DIAGRAMS
Timing Delays
HIGH
TXD
LOW
CANH
CANL
Dominant
0.9V
V
DIFF(BUS)
=
V
CANH
-
V
CANL
0.5V
Recessive
HIGH
RXD
t
dr(TXD)
t
df(TXD)
t
df(RXD)
t
Prop1
t
Prop2
t
dr(RXD)
50%
50%
LOW
TXD dominant time-out feature
t
dom(TXD)
recessive
TXD
dominant
transmitter disabled
CANH
CANL
transmitter
enabled
t
Rdom
HIGH
LOW
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HI-5000, HI-5001, HI-5002
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND = 0V)
Supply Voltage, VDD, VIO : .....................................................................7V
Current at Input pins ......................................................-100mA to +100mA
DC Voltages at TXD, RXD and STB ..............................-0.5V to V
DD
+0.5V
DC Voltages at CANH, CANL and SPLIT: ...............................-58V to +58V
Internal Power Dissipation: ..............................................................900mW
Electrostatic Discharge (ESD)
1
, All pins ..........................................+/- 6kV
Operating Temperature Range: (Industrial).........................-40°C to +85°C
Maximum Junction Temperature
2
......................................................175°C
Storage Temperature Range:
Soldering Temperature:
-65°C to +150°C
(Ceramic)......................60 sec. at +300°C
(Plastic - leads).............10 sec. at +280°C
(Plastic - body) .....................+260°C Max.
NOTES:
1. Human Body Model (HBM).
2. Junction Temperature T
J
is defined as T
J
= T
AMB
+ P × R
th
, where T
AMB
is the ambient or operating temperature, P is the power dissipation and R
th
is
a fixed thermal resistance value which depends on the package and circuit board mounting conditions.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
V
DD
= 5V
±
5%, Operating temperature range (unless otherwise noted). Positive currents flow into the IC.
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
V
DD
Supply Current
VIO Supply Current
I
DD
I
IO
Recessive: V
TXD
= V
DD
Dominant: V
TXD
= 0 V
Standby Mode: V
TXD
= V
DD
6
50
15
10
70
30
100
mA
mA
μA
μA
DIGITAL INPUTS (Pins TXD, STB)
HIGH-level input voltage (see Note 1)
LOW-level input voltage
HIGH-level input current
LOW-level input current
V
IH
V
IL
I
IH
I
IL
V
TXD
= V
DD
or VIO
V
TXD
= 0 V
70%V
DD
− 0.5
−5
0
− 50
V
DD
+ 0.5
30%V
DD
+5
− 150
V
V
μA
μA
DIGITAL OUTPUTS
HIGH-level output voltage (RXD Pin) (see Note 1)
LOW-level output voltage (RXD Pin)
Output voltage (SPLIT Pin)
Standby leakage current (SPLIT Pin)
V
OH
V
OL
V
SPLIT
I
STB
I
OH
= 1mA
I
OL
= 1mA
− 100 μA < I
SPLIT
< 100 μA
90%V
DD
0
0.45V
DD
-5
0.1
0.5V
DD
10%V
DD
0.55V
DD
+5
V
V
V
μA
DRIVER
CANH dominant output voltage
CANL dominant output voltage
Recessive output voltage
Bus output voltage in standby
Dominant differential output voltage
Recessive differential output voltage
Matching of dominant output voltage,
V
DD
− V
O(CANH)
− V
O(CANL)
Steady state common mode output voltage
V
O(CANH)
V
O(CANL)
V
CANH(r)
,
V
CANL(r)
V
STB
V
DIFF(d)(o)
V
DIFF(r)(o)
V
OM
V
OC(ss)
V
TXD
= 0 V
V
TXD
= 0 V (See Fig. 2)
V
TXD
= V
DD
, R
L
= 0 (See Fig. 2)
V
TXD
= V
DD
, R
L
= 0 (See Fig. 2)
V
TXD
= 0 V, 45 Ω < R
L
< 65 Ω
V
TXD
= V
DD
, no load (See Fig. 2)
(See Fig. 4)
V
STB
= 0V, R
L
= 60 Ω (See Fig. 5)
3
0.5
2
-0.1
1.5
− 50
− 100
2
1.8
0
-40
0.5V
DD
3.6
1.4
0.5V
DD
4.25
1.75
3
0.1
3
50
150
3
V
V
V
V
V
mV
mV
V
NOTE:
1. When VIO is connected (HI-5001 or HI-5002), limits are referenced wrt VIO rather than V
DD
.
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5
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