HI-3110, HI-3111, HI-3112, HI-3113
February 2017
Avionics CAN Controller
with Integrated Transceiver
FEATURES
·
Implements CAN version 2.0B with programmable bit
rate up to 1Mbit/sec. ISO 11898-5 compliant.
GENERAL DESCRIPTION
The HI-3110 is a standalone Controller Area Network
(CAN) controller with built in transceiver. The device
provides a complete, integrated, cost-effective solution for
avionics applications implementing the CAN 2.0B
specification and can be configured to comply with both the
ARINC 825 (General Standardization of CAN Bus Protocol
for Airborne Use) and CANaerospace standards. The HI-
3110 is capable of transmitting and receiving standard
data frames, extended data frames and remote frames.
The internal transceiver allows direct connection to the
CAN bus without using external components and coupled
with the host Serial Peripheral Interface (SPI), results in
minimal board space.
The HI-3110 provides the optimum solution for
applications where minimum host (MCU) overhead is
required, filtering unwanted messages using a maskable
identifier filter and storing up to 8 messages in the receive
FIFO. A flexible interrupt scheme allows real time
servicing of the FIFO by the host, if required.
Transmissions are handled using an 8 message transmit
FIFO. A Transmit Enable pin can be used by the host to
initiate a transmission. The device also provides monitor
or listen-only mode, low power sleep mode, loopback
mode for self-test and a re-transmission disable capability
(necessary to implement TTCAN protocol).
The HI-3111 is a digital only version of the HI-3110 (no
transceiver). This version provides a “protocol only”
solution for customers who wish to use an external
transceiver and may be used in situations where the
customer requires galvanic isolation between the bus and
digital protocol logic. The HI-3112 provides an option of a
CLKOUT pin instead of a SPLIT pin, which may be used as
the main system clock or as a clock input for other devices
in the system. Finally, the HI-3113 provides all options
(both CLKOUT and SPLIT pins) in a very compact QFN-44
package.
The HI-3110 family is available in industrial and full
extended temperature ranges, with a “RoHS compliant”
lead-free option. The design has been independently
validated by C&S group, GmbH, an ISO/IEC 17025
accredited test house. A copy of the test report is available
from Holt on request.
·
Configurable
to support ARINC 825 and
CANaerospace Standards.
·
Serial Peripheral Interface (SPI) (20MHz).
·
Standard, Extended and Remote frames supported.
·
8 maskable identifier filters.
·
Filtering on ID and first two data bytes for both
Standard and Extended Identifiers.
·
Loopback mode for self-test.
·
Monitor (Listen-only) and Low
Power Sleep Modes
with automatic wake-up possible.
·
8-message Transmit and Receive FIFOs.
·
Internal 16-bit free running counter for time tagging of
transmitted or received messages.
·
Permanent dominant timeout protection.
·
Short Circuit Protection of -58V to + 58V on CAN_H,
CAN_L and SPLIT pins (ISO 11898-5).
·
Re-transmission disable capability.
·
Transmit Enable pin.
·
Industrial and Full Extended temperature
supported:
Industrial: -40 C to + 85 C.
Extended: -55 C to + 125 C.
o
o
o
o
ranges
PIN CONFIGURATION (Top View)
VLOGIC 1
OSCOUT 2
OSCIN 3
GP1 4
GP2 5
TXEN 6
SPLIT 7
GND 8
CANL 9
18 INT
17 MR
16 CS
3110PSI
3110PST
3110PSM
15 SO
14 SI
13 SCK
12 STAT
11
VDD
10 CANH
18-Pin Plastic SOIC - WB Package
(DS3110 Rev. K)
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www.holtic.com
02/17
HI-3110, HI-3111, HI-3112, HI-3113
BLOCK DIAGRAM
VLOGIC
REGISTERS
CS
SPI BUS
SCK
SI
SO
SPI DECODE/
ENCODE
BIT
TIMING
GND
TRANSMIT
LOGIC & FIFO
TXEN
TXD
(HI-3111 only)
HISTORY
FIFO
GP2
GP1
STAT
INT
TRANSCEIVER
VDD
CANH
INTERRUPTS
AND
STATUS
ERROR
STATUS
& CONTROL
CANL
RECEIVE
LOGIC & FIFO
SPLIT
(see ordering
information)
FILTERS
OSCIN
OSCOUT
OSCILLATOR
16-BIT
TIME-TAG
COUNTER
(1,2,4,8-BIT
CLK DIV.)
RXD
(HI-3111 only)
MR
CLKOUT
(see ordering
information)
16-BIT
CLOCK DIV
OUT
Figure 1. Block Diagram
PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS
SPI PROTOCOL BLOCK
8 message FIFO with optional filters
Handles data transfers between the host and the chip Forwards message data and optional time stamp to the host
REGISTERS BLOCK
Stores configuration data
BIT TIMING BLOCK
Sets the data strobe and bit period
TRANSMIT BLOCK
Manages transmission protocol
8 message FIFO
Confirmation and time stamp of each message sent
is available in the History FIFO
RECEIVER BLOCK
Manages reception protocol
ERROR BLOCK
Detects and records errors for protocol management
STATUS AND INTERRUPT
Provides hardware and software options for managing
communications
OSCILLATOR
Configuration chooses either the crystal oscillator or and
external clock
TRANSCEIVER
Analog interface connects directly to the CAN bus
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HI-3110, HI-3111, HI-3112, HI-3113
PIN DESCRIPTIONS
SIGNAL
SCK
CS
SI
SO
INT
STAT
TXEN
FUNCTION
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
DESCRIPTION
NOTES
OSCIN
INPUT
OSCOUT
GP1
GP2
CLKOUT
SPLIT
CANH
CANL
TXD
RXD
MR
VDD
VLOGIC
GND
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
BUS I/O
BUS I/O
OUTPUT
INPUT
INPUT
POWER
POWER
POWER
SPI Clock. Data is shifted into or out of the SPI interface using SCK
50K ohm pull-down
Chip Select. Data is shifted into SI and out of SO when CS is low.
50K ohm pull-up
SPI interface serial data input
50K ohm pull-down
SPI interface serial data output
Active high. Programmable interrupt output
Active high. Programmable status output.
Active high. Transmit Enable pin. When the TXEN pin is asserted, any message 10
0K ohm pull-down
in the Transmit FIFO will be automatically loaded to the Transmit buffer and sent
if the bus is available. This pin is logically ORed with the TXEN and TX1M bits
in the CTRL1 register. When the TXEN pin is reset, messages loaded to the
FIFO will not be sent until TXEN or TX1M bits are set in the CTRL1 register.
Crystal input. A parallel resonant crystal can be connected between OSCIN and
OSCOUT. If an external clock is used, it should be connected to the OSCIN pin
and the OSCOUT pin should be left floating. The internal oscillator should be
shut off by setting the OSCOFF bit in the CTRL1 register.
Crystal output. If an external clock is used, this pin should be left floating and
disabled by setting the OSCOFF bit in the CTRL1 register.
General purpose pin 1, which can be programmed to reflect the values of
interrupt and status flag bits.
General purpose pin 2, which can be programmed to reflect the values of
interrupt and status flag bits.
Clock output pin with programmable frequency divider.
VDD/2 output bias (Powered off in Sleep Mode and when the common mode
bias is greater than 25V).
CAN bus line high.
CAN bus line low.
Transmit Data Out. Connect to TXD input pin on CAN transceiver (e.g. HI-3000).
HI-3111 only
Receive Data In. Connect to RXD output pin on CAN transceiver (e.g. HI-3000).
HI-3111 only
5V Logic Tolerant
Active High. Device Master Reset input pin. Asserting this pin resets all registers 50K ohm pull-down
and memory buffers to their default state at start-up.
5V supply voltage input.
3.3V supply voltage input. This supply is used to drive the host digital logic I/O.
It can either be connected directly to VDD (+5V) or a +3.3V supply.
Supply voltage ground.
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HI-3110, HI-3111, HI-3112, HI-3113
FUNCTIONAL OVERVIEW
The HI-3110 is the first single chip product to integrate both
the CAN (Controller Area Network) protocol and analog
interface transceiver on a single IC. The protocol conforms
to CAN version 2.0B and is compliant with ISO 11898-
1:2003(E) specification. The transceiver is compliant with
ISO 11898-5 specification.
Configuration options include an internal Loopback mode
that does not disturb the bus, a Monitor only mode, and a
Sleep mode that includes an option to either wake up
automatically when data is present on the bus, or by host
command. The following sections describe some of the key
features.
SPI and REGISTERS
To minimize the footprint, a 20 MHz standard four wire SPI
(Serial Peripheral Interface) is provided to manage the flow
of data between the host microcontroller and the HI-3110.
Complete messages are loaded and retrieved with single
SPI op codes. On the receive side, SPI op code options may
be used to retrieve the whole message or just the data. An
option to include a time tag or no time tag may also be
specified. On the transmit side, each message can be
assigned an identifier which allows monitoring of the
Transmit History FIFO to confirm the successful completion
of a transmission along with the time stamp. In addition the
transmitter logic automatically assembles the message
frame based on the data presented.
BIT TIMING
Bit timing is controlled with standard CAN options. These
include control of the Resychronization Jump Width (SJW),
Prop delay Phase Seg 1 (TSeg1), Phase Seg 2 (TSeg2), the
number of samples, and the derivation of Tq from the system
clock using a prescaler. The maximum bit rate is 1 MBit/sec.
Upon reset, the chip automatically enters Initialization mode
which allows programming of the Bit Timing before entering
Normal mode.
TRANSMITTER
The transmitter state machine automatically handles all
CAN 2.0B protocol requirements. Messages for
transmission are first loaded into a FIFO and transmission
may start upon availability of data in the FIFO. Assertion of
the TXEN pin or configuration bits in Control Register 1 allow
either continuous transmission until the FIFO is empty or
only one message from the FIFO at a time. One shot (no
retry) transmission may also be enabled by setting the OSM
and TX1M bits. SPI op codes are provided to clear the
Transmit FIFO and to abort transmission.
RECEIVER
The receiver state machine automatically handles all CAN
2.0B protocol requirements. The receiver supports eight
sets of filters and masks and each allows filtering of a full
CAN ID (extended or not) and two bytes of data. Even when
filtering is enabled, message data is always accessible as
received via the Temporary Receive Buffer, and retrievable
by SPI op codes 0x42 and 0x44.
If the Filter/Mask option is set (FILTON bit in Control Register
1), only messages that match one of the 8 stored data
patterns are passed into the FIFO. Note that the Mask option
allows certain bits of the programmed filter bits to be “don't
care.” If the Filter/Mask option is not set, then all valid
messages are passed to the FIFO. When the FIFO is full (8
completed messages received), the next received message
is not loaded in the FIFO.
ERROR CONTROL
Errors are detected per ISO 11898-1:2003(E) and
detections are counted and used by the protocol state
machines. Active, Passive, and Bus Off conditions are
managed per the CAN standard. A configuration bit is
provided to allow automatic recovery from Bus Off.
STATUS and INTERRUPTS
The Message Status Register, MESSTAT, provides
information about the current state of the receiver and
transmitter operation. In addition, the Interrupt Flag
Register, INTF, monitors 8 operational conditions, any or all
of which may be directed to the INT pin by enabling bits in the
Interrupt Enable Register, INTE. Similarly, the Status Flag
Register, STATF, bits reflect the status of selected FIFO and
Error properties. Any or all of these conditions may be
directed to the STAT pin by setting the enable bits in the
Status Flag Enable Register, STATFE.
To provide additional hardwired flag options, the GP1 and
GP2 pins may also be programmed to reflect any of the
Interrupt or Status Flag bits.
OSCILLATOR and TIME TAG
A configuration bit allows a choice for the source of the
system clock. Either the on-board crystal oscillator may be
selected or an external clock may be provided at the OSCIN
pin.
On product versions with the CLKOUT pin, a programmable
division of the system clock is provided. The clock source for
the 16 bit Time Tag Counter is derived from a separate
programmable division of the system clock. SPI op codes
provide for reading and resetting the Time Tag Counter.
TRANSCEIVER
The HI-3110 contains an integrated transceiver operating
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HI-3110, HI-3111, HI-3112, HI-3113
from 5V and the line driver is capable of maintaining a
detectable signal for bus lengths well in excess of
recommended CAN 2.0B standards. The digital logic and IO
can be powered from 3.3V or 5V.
PROTECTION FEATURES
The BUS and SPLIT pins are protected against ESD to over
4KV (HBM) and from shorts between -58V to +58V
continuous, as specified in ISO 11898-5.
In addition, a Permanent Dominant Timeout protection is
implemented by means of an independent counter
monitoring the dominant transmission state and
automatically shutting off the transmission if it exceeds
typically 2ms.
MONITOR MODE
Monitor mode (also known as listen-only or silent mode)
allows the HI-3110 to monitor all bus activity without
disturbing the bus. No messages or dominant bits (such as
ACK or active error frame bits) are transmitted to the bus
while in this mode. Also, the error counters are reset and
deactivated. Messages from the bus are received in the
same way as Normal Mode and messages that are not
acknowledged by another node on the bus are ignored i.e.
any frame containing an error will be ignored. Acceptance
filters can be set up to reject or accept specific messages
into the FIFO and all interrupt flags are set as required in the
usual way. Monitor mode is activated by programming the
MODE<2:0> bits to <010> in the CTRL0 register.
SLEEP MODE
MODES OF OPERATION
The HI-3110 supports five modes of operation, namely,
Initialization Mode, Normal Mode, Loopback Mode, Monitor
Mode and Sleep Mode.
INITIALIZATION MODE
Initialization mode is used to configure the device before
normal operation.
Bit timing registers and acceptance
filters and masks can only be modified in this mode.
Initialization mode is the default mode following RESET and
can also be activated by programming the MODE<2:0> bits
to <1xx> in the CTRL0 register. Switching to Initialization
mode resets the receiver and transmitter. During
initialization mode, the error counters are held reset.
The HI-3110 can be placed in a low power sleep mode if
there is no bus activity and the transmit FIFO is empty. In
this mode, the internal oscillator and all analog circuitry
(transceiver) are off, drawing typically less than 20
m
A. Note
that the SPI bus is active during sleep mode, so it is possible
for the host to communicate with the HI-3110 while it is
asleep (e.g. load transmit FIFO). Sleep mode is exited by
selecting an alternative mode of operation, or automatic
wake up following bus activity can be enabled by setting the
WAKEUP bit in the CTRL0 register - in this case a low power
receiver monitors the bus for a detectable dominant bit..
The device will wake up in Monitor Mode. Note that it will
take a finite time for the oscillator and analog circuitry to
come back on line. Since the internal oscillator takes a finite
time to wake up, the message which caused the wake-up
may not be stored.
Sleep mode is activated by programming the MODE<2:0>
bits to <011> in the CTRL0 register. However, the actual
mode change will only occur whenever the CAN bus is quiet.
If the chip is transmitting, the mode change is delayed until
the transmission is complete. If there is bus activity, the
mode change is delayed until the receiver protocol control
detects an inter-message gap.
NORMAL MODE
Normal mode is the standard operating mode of the HI-3110.
In this mode, the HI-3110 can transmit, receive and
acknowledge messages from the CAN bus, handling all
aspects of the CAN protocol. Normal mode is activated by
programming the MODE<2:0> bits to <000> in the CTRL0
register.
LOOPBACK MODE
Loopback mode is used for self-test. The transceiver digital
input is fed back to the receiver without being transmitted to
the bus. Messages are transmitted from the transmit FIFO
in the usual way and received by the receive FIFO as if they
were received from a remote node on the bus.
Acceptance filters can be set up to accept or reject specific
messages into the FIFO and all interrupt flags are set as
required in the usual way. While in this mode, any bus
activity is ignored. Loopback is activated by programming
the MODE<2:0> bits to <001> in the CTRL0 register.
CAN PROTOCOL OVERVIEW
The HI-3110 supports Standard, Extended and Remote
Frames, as defined in the CAN specification IS0 11898-
1:2003(E) (also known as CAN 2.0B).
BIT ENCODING
CAN frames are encoded according to the Non-Return-To-
Zero (NRZ) method with bit stuffing. NRZ means that the
generated bit level is constant during the total bit time and
consecutive bits do not return to a neutral or rest condition.
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