N-Channel Synchronous MOSFETs With Break-Before-Make
DESCRIPTION
The Si4724CY N-Channel synchronous MOSFET with
break-before-make (BBM) is a high speed driver designed to
operate in high frequency DC/DC switchmode power
supplies. It’s purpose is to simplify the use of N-Channel
MOSFETs in high frequency buck regulators. This device is
designed to be used with any single output PWM IC or ASIC
to produce a highly efficient low cost synchronous rectifier
converter. A synchronous enable pin (disable = low,
enable = high) controls the synchronous function for light
load conditions.
The Si4724CY is packaged in Vishay Siliconix’s high
performance LITTLE FOOT
®
SO-16 package.
FEATURES
•
•
•
•
•
•
•
•
•
0 V to 30 V operation
Driver impedance-3
Undervoltage lockout
Fast switching times
30 V MOSFETs
High side: 0.0375 at V
DD
= 4.5 V
Low side: 0.029 at V
DD
= 4.5 V
Switching frequency: 250 kHz to 1 MHz
Integrated schottky
Available
FUNCTIONAL BLOCK DIAGRAM
V
DD
BOOT
D
1
Level Shift
Undervoltage
Lockout
V
DD
IN
SYNC EN
Q
1
S
1
D
2
Q
2
+
-
S
2
V
REF
GND
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
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1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si4724
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
Parameter
Logic Supply
Logic Inputs
Drain Voltage
Bootstrap Voltage
Synchronous pin Voltage
T
A
= 25 °C
Continuous Drain Current
T
A
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Driver
MOSFETs
Symbol
V
DD
V
IN
V
D1
V
BOOT
V
SYNC
I
D1
I
D2
P
D
T
J
, T
stg
Steady State
7
- 0.7 to V
DD
+ 0.3
30
V
S1
+ 7
- 0.7 to V
DD
+ 0.3
5.1
4.09
6.5
5.2
1.2
- 65 to 125
- 65 to 150
W
°C
A
V
Unit
Notes:
a. Surface mounted on 1" x 1" FR4 board, full copper two sides.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain Voltage
Logic Supply
Input Logic High Voltage
Input Logic Low Voltage
Bootstrap Capacitor
Ambient Temperature
Symbol
V
D1
V
DD
V
IH
V
IL
C
BOOT
T
A
Steady State
0 to 30
4.5 to 5.5
0.7 x V
DD
to V
DD
- 0.3 to 0.3 x V
DD
0.1 to 1
- 40 to 85
µ
°C
V
Unit
THERMAL RESISTANCE RATINGS
Parameter
Highside Junction-to-Ambient
a
Lowside Junction-to-Ambient
a
Highside Junction-to-Foot (Drain)
b
Lowside Junction-to-Foot (Drain)
b
Steady State
Symbol
R
thJA1
R
thJA2
R
thJF1
R
thJF2
Typical
85
68
28
19
Maximum
105
85
35
24
°C/W
Unit
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in
conjunction with the thermal impedance of the PC board pads to ambient (R
thJA
= R
thJF
+ R
thPCB-A
). It can also be used to estimate chip tem-
perature if power dissipation and the lead temperature of a heat carrying (drain) lead is known.
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Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si4724
Vishay Siliconix
SPECIFICATIONS
Parameter
Power Supplies
Logic Voltage
Logic Current
Logic Input
Logic Input Voltage (V
IN
)
Protection
Break-Before-Make Reference
Undervoltage Lockout
Undervoltage Lockout Hysteresis
MOSFET Drivers
Driver Impedance
MOSFETs
Drain-Source Voltage
Drain Source On State Resistance
a
Diode Forward Voltage
a
V
DS
R
DS(on)1
R
DS(on)2
V
SD1
V
SD2
I
D
= 250 µA
V
DD
= 4.5 V, I
D
= 5 A
T
A
= 25 °C
I
S
= 2 A, V
GS
= 0
Q1
Q2
Q1
Q2
30
30
24
0.7
0.7
37.5
29
1.1
1.1
V
mΩ
V
R
DR1
R
DR2
V
DD
= 4.5 V
Driver 1
Driver 2
3
2
V
V
BBM
V
UVLO
V
H
V
DD
= 5.5
SYNC = 4.5
3.75
2.4
4
0.4
4.25
V
High
Low
V
IH
V
IL
V
DD
= 4.5
- 40 °C
≤
T
A
≤
85 °C
3.15
- 0.3
2.3
2.25
0.8
V
V
DD
I
DD(EN)
I
DD(DIS)
V
DD
= 4.5 V, V
IN
= 4.5 V
V
DD
= 4.5 V, V
IN
= 0 V
4.5
280
220
5.5
500
500
V
µA
Symbol
Test Conditions Unless Specified
T
A
= 25 °C
4.5 V < V
DD
< 5.5 V, 4.5 V < V
D1
< 30 V
Limits
Min.
Typ.
Max.
Unit
Dynamic
b
(Unless Specified-F
s
= 250 kHz, V
IN
= 12 V. V
DD
= 5 V, I = 5 A, Refer to Switching Test Setup)
Turn Off Delay
Δt
Source-Drain Reverse Recovery
Time-Q
2
t
d(off)1
t
d(off)2
Δt
1-2
Δt
2-1
t
frr
See Timing Diagram
V
IN
to G
1
V
IN
to G
2
G
1
to G
2
G
2
to G
1
I
F
2.7 A, di/dt = 100 A/µs
28
17
16
38
50
56
40
32
80
80
ns
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SCHOTTKY SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
Parameter
Forward Voltage Drop
Symbol
V
F
Test Conditions
I
F
= 1 A
I
F
= 1 A, T
J
= 125 °C
V
r
= 30 V
Maximum Reverse Leakage Current
Junction Capacitance
I
rm
C
T
V
r
= 30 V, T
J
= 100 °C
V
r
= - 30 V, T
J
= 125 °C
V
r
= 10 V
Min
Typ
0.47
0.36
0.004
0.7
3
50
Max
0.50
0.42
0.100
10
20
pF
mA
Unit
V
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si4724
Vishay Siliconix
APPLICATION CIRCUIT
0 V to 30 V
5V
V
DD
Si4724
C
BOOT
D
1
Q
1
MOSFET
Drive Circuitry
with
Break-Before-
Make
S
1
D
2
C
BOOT
V
OUT
+
SYNC EN
DC-DC
Controller
IN
GND
Q
2
S
2
GND
GND
Power Up Sequence:
Ensure V
DD
is within spec before allowing IN or SYNC EN to be set high.
Power Down Sequence:
Ensure IN and SYNC EN are low before turning V
DD
off.
Figure 1.
PIN CONFIGURATION
TRUTH TABLE
Sync EN
H
CLK
H
L
H
L
Q
1
ON
OFF
ON
OFF
Q
2
OFF
ON
OFF
OFF
SO-16
D
1
D
1
GND
IN
SYNC EN
S
2
S
2
S
2
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
S
1
S
1
C
BOOT
V
DD
D
2
D
2
D
2
D
2
H
L
L
PIN DESCRIPTION
Pin
Number
1, 2
3
4
5
6, 7, 8
9, 10, 11, 12
13
Symbol
D
1
GND
IN
S
2
D
2
V
DD
C
BOOT
S
1
Description
Highside MOSFET Drain
Ground
Input Logic Signal
Lowside MOSFET Source
Lowside MOSFET Drain
Logic Supply, decoupling to GND with
a cap is strongly recommended.
Bootstrap Capacitor for Upper
MOSFET
Highside MOSFET Source
SYNC EN Synchronous Enable
Ordering Information:
Si4724CY-T1
Si4724CY-T1-E3 (Lead (Pb)-free)
14
15, 16
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Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Si4724
Vishay Siliconix
TIMING DIAGRAM
IN
IN
G
1
G
2
G
2
G
1
t
d(off)
output
(S
1
/D
2
, not to scale)
Δt
1- 2
t
d(off)
Δt
2-1
output
(S
1
/D
2
, not to scale)
Figure 2.
Δt
1-2
Figure 3.
Δt
2-1
SWITCHING TEST SET-UP
12 V
C
V
DD
5V
D
1
C
G
1
C
BOOT
MOSFET
Drive Circuitry
with
Break-Before-
Make
S
1
G
2
D
2
S
1
/D
2
C
L
S
2
GND
+
R
L
L
C
BOOT
SYNC EN
IN
Signal Input
GND
GND
Figure 4.
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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