SiC714CD10
Vishay Siliconix
Fast Switching MOSFETs With Integrated Driver
PRODUCT SUMMARY
Input Voltage Range
Output Voltage Range
Operating Frequency
Continuous Output Current
Peak Efficiency
Optimized Duty Cycle Ratio
3.3 to 15 V
0.5 to 6 V
100 kHz to 1 MHz
Up to 27 A
> 94 % at 300 kHz
10 %
FEATURES
• Low-side MOSFET control pin for
prebias start-up
• Undervoltage Lockout for safe operation
• Internal boostrap diode reduces
component count
• Break-Before-Make operation
• Turn-on/Turn-off Capability
• Compatible with any single or multi-phase PWM
controller
• Low profile, thermally enhanced PowerPAK
®
MLF
10 x 10 Package
PowerPAK MLF 10 x 10
1
APPLICATIONS
• DC-to-DC Point-of-Load Converters
- 3.3 V, 5 V, or 12 V Intermediate BUS
- Examples
- 12 V
IN
/0.8 - 2.5 V
OUT
- 5 V
IN
/0.8 - 1.5 V
OUT
• Servers and Computers
Bottom View
Ordering Information:
SiC714CD10-T1
SiC714CD10-T1-E3 (Lead (Pb)-free)
*see page 2 for peak temperature
•
Single and Multi-Phase Conversion
DESCRIPTION
The SiC714CD10 is an integrated solution which contains
two PWM-optimized MOSFETs (high side and low side
MOSFETs) and a driver IC. Integrating the driver allows bet-
ter optimization of Power MOSFETs. This minimizes the
losses and provides better performance at higher frequency.
The SiC714CD10 is packed in Vishay Siliconix’s high perfor-
mance PowerPAK MLF 10 x 10 package. Compact copack-
ing of components helps to reduce stray inductance, and
hence increases efficiency.
FUNCTIONAL BLOCK DIAGRAM
C
BOOT
V
IN
UVLO
V
DD
SHDN
+
-
BBM
SW
V
DD
PWM
SYNC
CGND
PGND
Figure 1.
* Pb containing terminations are not RoHS compliant, exemptions may apply.
Document Number: 73569
S-62659–Rev. C, 25-Dec-06
www.vishay.com
1
SiC714CD10
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Logic Supply
Logic Inputs
Common Switch Node
Drain Voltage
Bootstrap Voltage
Maximum Power Dissipation (Measured at 25 °C )
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
a, b
Symbol
V
DD
V
PWM
V
SW
V
IN
V
BOOT
P
D
T
j
, T
stg
Steady State
7
7.3
30
30
SW + 7
6
- 65 to 125
240
W
°C
V
Unit
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain Voltage
Logic Supply
Input Logic PWM Voltage
Bootstrap Capacitor
Symbol
V
IN
V
DD
V
PWM
C
BOOT
Steady State
3.0 to 15
4.5 to 5.5
5
100 n to 1 µ
Unit
V
F
THERMAL RESISTANCE RATINGS
Parameter
c
Maximum Junction-to-Case
Maximum Junction-to-Ambient
(PCB = Copper 25 mm x 25 mm)
Symbol
R
thJC
Steady State
R
thJA
Typical
2.1
50
Maximum
2.6
75
Unit
°C/W
Notes:
a. See Reliability Manual for profile. The PowerPAK MLF 10 x 10 is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot guaranteed and is not required
to ensure adequate bottom side soldering interconnection.
b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use
in conjunction with the thermal impedance of the PC board pads to ambient (R
thJA
= R
thJC
+ R
thPCB-A
). It can also be used to estimate chip
temperature if power dissipation and the lead temperature of heat carrying (drain) lead is known.
www.vishay.com
2
Document Number: 73569
S-62659–Rev. C, 25-Dec-06
SiC714CD10
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
T
A
= 25 °C
4.5 V < V
DD
< 5.5 V, 4.5 V < V
D1
< 20 V
Limits
Min
4.5
V
DD
= 4.5 V, SYNC = H, PWM = H, SHDN = H
V
DD
= 4.5 V, SYNC = H, PWM = H, SHDN = L
V
DD
= 5 V, f
clk
= 250 kHz
c
V
DD
= 5 V, f
clk
= 0.7 MHz
c
2.5
1.35
2.0
2.0
400
V
DD
= 5.5 V, SHDN = 0 V
V
DD
= 5.5 V, PMW = 5.5 V
V
DD
= 5.5 V
V
DD
= 5 V, SYNC = H, SHDN = H
3.5
117
120
2.4
4
0.4
20
High-Side
Low-Side
High-Side
Low-Side
22
10.2
3
0.7
0.67
12.75
3.6
1.1
1.1
mΩ
V
V
4.25
V
mV
µA
V
1166
120
27.5
mA
59.5
Typ
a
Max
5.5
Unit
V
µA
Parameter
Controller
Logic Voltage
Logic Current (Static)
Symbol
V
DD
I
DD(EN)
I
DD(DIS)
I
DD1(DYN)
I
DD2(DYN)
Logic Current (Dynamic)
Logic Input
Logic Input (VPWM)
Logic Input Voltage (V
SYNC
)
Logic Input Voltage (V
SHDN
)
Input Voltage Hysteresis (PWM)
Logic Input Current
Protection
Break-Before-Make Reference
Under-Voltage Lockout
Under-Voltage Lockout Hysteresis
MOSFETs
Drain-Source Voltage
Drain-Source On-State
Resistance
a
Diode Forward Voltage
a
Dynamic
b, c
Turn On Delay Time
Turn Off Delay Time
High
Low
V
PWMH
V
PWML
V
SYNC
V
SHDN
V
HYS
I
SHDN
I
PWM
V
BBM
V
UVLO
V
H
V
DS
r
DS(on)1
r
DS(on)2
V
SD1
V
SD2
t
d(on)
t
d(off)
V
DD
= 5 V, SYNC = H, SHDN = H
V
DD
= 5 V, PMW = H, SHDN = H
V
DD
= 5 V, PMW = H, SYNC = H
I
D
= 250 µA
V
DD
= 5 V, I
D
= 10 A
T
A
= 25 °C
I
S
= 2 A, V
GS
= 0 V
50 % - 50 %
c
66
32
ns
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Using application board SiDB766707.
Document Number: 73569
S-62659–Rev. C, 25-Dec-06
www.vishay.com
3
SiC714CD10
Vishay Siliconix
TIMING DIAGRAM
SHDN
SYNC
PWM
HS MOSFET
Gate
LS MOSFET
Gate
SW
t
d(on)
t
d(off)
Figure 2.
APPLICATION INFORMATION
(25 °C, unless noted, LFM = 0)
94
92
300 kHz
90
Total Loss (
W
)
Efficiency (
%
)
88
86
84
82
80
78
76
0
10
20
30
Output Current – (A)
500 kHz
700 kHz
7
6
5
500 kHz
4
3
2
1
0
0
5
10
15
20
25
30
Output Current – (A)
300 kHz
700 kHz
9
8
Figure 3. Total Efficiency 12V
IN
/1.3 V
OUT
Notes:
a. Experimental results using an evaluation board with a specific set of operating conditions.
Figure 4. Total Loss 12 V
IN
/1.3 V
OUT
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4
Document Number: 73569
S-62659–Rev. C, 25-Dec-06
SiC714CD10
Vishay Siliconix
PIN CONFIGURATION
PowerPAK MLF 10 mm x 10 mm (Bottom View)
S
W
S
W
S
W
S
W
S
W
S
W
S
W
S
W
S
W
V
I
N
V
I
N
V
I
N
V
I
N
V
I
N
V
I
N
V
I
N
62
N
C
61
5
8
56
55
52
53
54
57
59
60
65
66
64
67
63
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
(SW)
CGND
Driver
Tab
Low-Side
MOS Tab
V
IN
High-Side
MOS Tab
6
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
NC
CGND
C
BOOT
NC
C
BOOT
V
DD
NC
NC
25
23
1
8
27
26
24
22
21
20
19
32
30
2
8
33
N
C
31
29
34
N
C
SW
N
C
CG
N
D
P
W
M
N
C
V
DD
N
C
V
DD
N
C
SY
N
C
N
C
N
C
N
C
N
C
SHD
N
TRUTH TABLE
SHDN
L
H
H
H
H
SYNC
X
L
L
H
H
PWM
X
L
H
L
H
HS MOSFET
OFF
OFF
ON
OFF
ON
LS MOSFET
OFF
OFF
OFF
ON
OFF
PIN DESCRIPTION
Pin Number
1 - 9, 62 - 68
10, 13, 16 - 18, 20, 22, 25,
11, 24
11, 24
12, 14
15, 19, 21
23
27
28
35 - 51
26, 52 - 60
Symbol
V
IN
NC
CGND
C
BOOT
V
DD
PMW
SYNC
SHDN
PGND
SW
Description
Input-Voltage (High-Side MOSFET Drain)
No Connect
Control Ground. Should be connected to PGND externally
Contol Ground. Should be connected to PGND externally
Connection pin for Bootstrap Capacitor for Upper MOSFET
Logic Supply Voltage - decoupling to GND with a CAP is strongly recommended
Pulse Width Modulation (PWM) Signal Input
Disable Low-Side MOSFET Drive
Disable All Functions (Active Low)
Power Ground (Low-Side MOSFET Source)
Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain)
Document Number: 73569
S-62659–Rev. C, 25-Dec-06
www.vishay.com
5
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