d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 54 °C/W.
Document Number: 65253
S11-1651-Rev. B, 15-Aug-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
New Product
SiR662DP
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
a
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
I
F
= 10 A, dI/dt = 100 A/µs, T
J
= 25 °C
I
S
= 5 A
0.73
147
245
72
75
T
C
= 25 °C
60
100
1.1
250
400
A
V
ns
nC
ns
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 30 V, R
L
= 3
I
D
10 A, V
GEN
= 4.5 V, R
g
= 1
V
DD
= 30 V, R
L
= 3
I
D
10 A, V
GEN
= 10 V, R
g
= 1
f = 1 MHz
0.4
V
DS
= 30 V, V
GS
= 10 V, I
D
= 20 A
V
DS
= 30 V, V
GS
= 4.5 V, I
D
= 20 A
V
DS
= 30 V, V
GS
= 0 V, f = 1 MHz
4390
2230
327
64
30
11.6
7.2
1.2
17
12
40
12
60
95
45
30
2.4
34
24
80
24
120
180
90
60
ns
96
45
nC
pF
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0 V, V
GS
= ± 20 V
V
DS
= 60 V, V
GS
= 0 V
V
DS
= 60 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
5
V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 20 A
V
GS
= 4.5 V, I
D
= 20 A
V
DS
= 15 V, I
D
= 20 A
30
0.0022
0.0029
93
0.0027
0.0035
1
60
28
-6
2.5
± 100
1
10
V
mV/°C
V
nA
µA
A
S
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 65253
S11-1651-Rev. B, 15-Aug-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
New Product
SiR662DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
80
V
GS
= 10 V thru 4 V
64
I
D
- Drain Current (A)
10
8
I
D
- Drain Current (A)
48
V
GS
= 3 V
32
6
4
T
C
= 25 °C
2
T
C
= 125 °C
16
V
GS
= 2 V
0.5
1.0
1.5
2.0
2.5
0
0.0
0
0
1
T
C
= - 55 °C
2
3
4
V
GS
- Gate-to-Source Voltage (V)
5
V
DS
- Drain-to-Source Voltage (V)
Output Characteristics
0.0035
5000
Transfer Characteristics
C
iss
0.0031
C - Capacitance (pF)
R
DS(on)
- On-Resistance (Ω)
4000
V
GS
= 4.5 V
0.0027
3000
C
oss
2000
0.0023
V
GS
= 10 V
0.0019
1000
C
rss
0.0015
0
16
32
48
64
80
I
D
- Drain Current (A)
0
0
12
24
36
48
60
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
10
R
DS(on)
- On-Resistance (Normalized)
Capacitance
2.0
I
D
= 20 A
V
GS
- Gate-to-Source Voltage (V)
I
D
= 20 A
1.7
V
GS
= 10 V
1.4
V
GS
= 4.5 V
1.1
8
V
DS
= 30 V
6
V
DS
= 20 V
V
DS
= 40 V
4
2
0.8
0
0
14
28
42
56
70
Q
g
- Total Gate Charge (nC)
0.5
- 50
- 25
0
25
50
75
100
125
150
T
J
- Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 65253
S11-1651-Rev. B, 15-Aug-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
New Product
SiR662DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
100
0.015
I
D
= 20 A
10
T
J
= 150 °C
1
R
DS(on)
- On-Resistance (Ω)
0.012
I
S
- Source Current (A)
0.009
0.1
T
J
= 25 °C
0.006
T
J
= 125 °C
0.003
T
J
= 25 °C
0.01
0.001
0.0
0.000
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
6
8
10
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
0.5
On-Resistance vs. Gate-to-Source Voltage
200
0.2
V
GS(th)
Variance (V)
160
I
D
= 5 mA
- 0.4
I
D
= 250 μA
- 0.7
Power (W)
- 0.1
120
80
40
- 1.0
- 50
0
- 25
0
25
50
75
100
125
150
0.001
0.01
T
J
- Temperature (°C)
0.1
Time (s)
1
10
Threshold Voltage
100
Limited by R
DS(on)
*
Single Pulse Power, Junction-to-Ambient
1 ms
10
I
D
- Drain Current (A)
10 ms
1
100 ms
1s
0.1
T
A
= 25 °C
Single Pulse
0.01
0.01
BVDSS Limited
10 s
DC
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
www.vishay.com
4
Document Number: 65253
S11-1651-Rev. B, 15-Aug-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
New Product
SiR662DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
200
160
I
D
- Drain Current (A)
120
80
Package Limited
40
0
0
25
50
75
100
125
150
T
C
- Case Temperature (°C)
Current Derating*
125
3.0
100
2.4
Power (W)
50
Power (W)
75
1.8
1.2
25
0.6
0
0
25
50
75
100
125
150
T
C
- Case Temperature (°C)
0.0
0
25
50
75
100
125
150
T
A
- Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
* The power dissipation P
D
is based on T
J(max)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 65253
S11-1651-Rev. B, 15-Aug-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
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xi 在国际测试大会上，英特尔公司副总裁兼副总经理Gadi Singer在题为“应对频谱纳米技术和千兆复杂性的挑战”的演讲中指出，从1940年以来，每立方英尺MIPS或每磅MIPS数每10年就增加100倍。虽然在平滑的曲线上一直是以指数规律变化，但是，在那个时期仍然有许多不连续性和变形点。 “目前，四个不同的趋势正延伸在所有方向中的曲线，”Singer说道。首先，IC复杂性和多样性...[详细]
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