Rad-Hard 16 Channel CMOS Analog Multiplexer with
High-Z Analog Input Protection
HS-1840ARH, HS-1840AEH,
HS-1840BRH
TheHS-1840ARH, HS-1840AEH, HS-1840BRH are radiation hardened,
monolithic 16 channel multiplexers constructed with the Intersil Rad-
Hard Silicon Gate, bonded wafer, Dielectric Isolation process. They are
designed to provide a high input impedance to the analog source if
device power fails (open), or the analog signal voltage inadvertently
exceeds the supply by up to
±35V,
regardless of whether the device is
powered on or off. Excellent for use in redundant applications, since the
secondary device can be operated in a standby unpowered mode
affording no additional power drain. More significantly, a very high
impedance exists between the active and inactive devices preventing
any interaction. One of sixteen channel selections is controlled by a 4-bit
binary address plus an Enable-Inhibit input which conveniently controls
the ON/OFF operation of several multiplexers in a system. All inputs
have electrostatic discharge protection. The HS-1840ARH,
HS-1840AEH, HS-1840BRH are processed and screened in full
compliance with MIL-PRF-38535 and QML standards. The devices are
available in a 28 Ld SBDIP and a 28 Ld Ceramic Flatpack.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are contained in
SMD 5962-95630. A “hot-link” is provided on our homepage for
downloading:
http://www.landandmaritime.dla.mil/Downloads/MilSpec/Smd/956
30.pdf
Features
• Electrically Screened to SMD # 5962-95630
• QML Qualified per MIL-PRF-38535 Requirements
• Pin-to-Pin for Intersil’s HS-1840RH and HS-1840/883S
• Improved Radiation Performance
- Gamma Dose (γ) 3x10
5
RAD(Si)
• Improved r
DS(ON)
Linearity
• Improved Access Time 1.5µs (Max) Over Temp and Post Rad
• High Analog Input Impedance 500MΩ During Power Loss (Open)
•
±35V
Input Overvoltage Protection (Power On or Off)
• Dielectrically Isolated Device Islands
• Excellent in Hi-Rel Redundant Systems
• Break-Before-Make Switching
• No Latch-Up
November 17, 2011
FN4355.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2002, 2009, 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-1840ARH, HS-1840AEH, HS-1840BRH
Burn-In/Life Test Circuits
R
+V
S
R
1
2
3
4
5
6
7
8
9
10
GND
F4
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
F1
F2
F3
F5
GND
V
R
R
-V
S
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-V
S
R
R
NOTE:
V
S
+ = +15.5V ±0.5V, V
S
- = -15.5V ±0.5V.
R = 1kΩ ±5%.
C
1
= C
2
= 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM.
D
1
= D
2
= 1N4002, 1 EACH PER BOARD, MINIMUM.
INPUT SIGNALS:
SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
NOTE:
R = 1kΩ ±5%, 1/4W.
C
1
= C
2
= 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.
V
S
+ = 15.5V ±0.5V, V
S
- = -15.5V ±0.5V, V
R
= 15.5 ±0.5V
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH, HS-1840AEH, HS-1840BRH
+15V
NC
NC
+1V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-15V
1kΩ
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
4
FN4355.4
November 17, 2011
HS-1840ARH, HS-1840AEH, HS-1840BRH
Die Characteristics
DIE DIMENSIONS:
(2820µmx4080µm x 483µm
±25.4μm)
111 milsx161 milsx19 mils
±1
mil
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8.0k
Å
±1k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
±2k
Å
Backside Finish:
Silicon
ADDITIONAL INFORMATION:
Worst Case Current Density:
Modified SEM
Transistor Count:
407
Process:
Radiation Hardened Silicon Gate,
Bonded Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH, HS-1840BRH
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN8
ENABLE
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
5
IN10
IN11
IN9
FN4355.4
November 17, 2011
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
