Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
gd
model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72423
09-Jun-04
www.vishay.com
1
SPICE Device Model SUM110N03-04P
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
V
GS(th)
I
D(on)
a
Symbol
Test Conditions
Simulated
Data
1.8
1375
0.0033
0.0049
0.0058
0.0052
70
0.92
Measured
Data
Unit
V
DS
= V
GS
, I
D
= 250
µA
V
DS
= 5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 20 A
V
A
0.0033
Ω
Drain-Source On-State Resistance
r
DS(on)
V
GS
= 10 V, I
D
= 20 A, T
J
= 125°C
V
GS
= 10 V, I
D
= 20 A, T
J
= 175°C
V
GS
= 4.5 V, I
D
= 20 A
0.0052
S
1.2
V
Forward Transconductance
a
Forward Voltage
a
g
fs
V
SD
V
DS
= 15 V, I
D
= 20 A
I
S
= 100 A, V
GS
= 0 V
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
c
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
c
5194
V
GS
= 0 V, V
DS
= 25 V, f = 1 MHz
780
292
43
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 50 A
18
16
13
V
DD
= 15 V, R
L
= 0.30
Ω
I
D
≅
50 A, V
GEN
= 10 V, R
G
= 2.5
Ω
15
31
31
5100
860
430
40
18
16
12
12
40
10
Ns
NC
Pf
Gate-Source Charge
c
Gate-Drain Charge
c
Turn-On Delay Time
Rise Time
c
Turn-Off Delay Time
Fall Time
c
t
d(on)
t
r
c
t
d(off)
t
f
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
2
Document Number: 72423
09-Jun-04
SPICE Device Model SUM110N03-04P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 72423
09-Jun-04
www.vishay.com
3
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
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