TS5070
TS5071
PROGRAMMABLE CODEC/FILTER
COMBO 2
ND
GENERATION
COMPLETE CODEC AND FILTER SYSTEM
INCLUDING :
– TRANSMIT AND RECEIVE PCM CHANNEL
FILTERS
–
µ-LAW
OR A-LAW COMPANDING CODER
AND DECODER
– RECEIVE POWER AMPLIFIER DRIVES
300
Ω
– 4.096 MHz SERIAL PCM DATA (max)
PROGRAMMABLE FUNCTIONS :
– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– HYBRID BALANCE CANCELLATION FIL-
TER
– TIME-SLOT ASSIGNMENT: UP TO 64
SLOTS/FRAME
– 2 PORT ASSIGNMENT (TS5070)
– 6 INTERFACE LATCHES (TS5070)
– A OR
µ
-LAW
– ANALOG LOOPBACK
– DIGITAL LOOPBACK
DIRECT INTERFACE TO SOLID-STATE
SLICs
SIMPLIFIES TRANSFORMER SLIC, SINGLE
WINDING SECONDARY
STANDARD SERIAL CONTROL INTERFACE
80 mW OPERATING POWER (typ)
1.5mW STANDBY POWER (typ)
MEETS OR EXCEEDS ALL CCITT AND
LSSGR SPECIFICATIONS
TTL AND CMOS COMPATIBLE DIGITAL IN-
TERFACES
DESCRIPTION
The TS5070series are the second generationcom-
bined PCM CODEC and Filter devices optimized
for digital switching applications on subscriber and
trunk line cards.
Using advanced switched capacitor techniques the
TS5070 and TS5071 combine transmit bandpass
and receive lowpass channel filters with a com-
panding PCM encoder and decoder. The devices
are A-law and
µ-law
selectable and employ a con-
ventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programma-
ble functions may be controlled via a serial control
port.
December 1997
DIP20
(Plastic)
ORDERING NUMBER:TS5071N
PLCC28
ORDERING NUMBERS:
TS5070FN
TS5070FNTR
Channel gains are programmable over a 25.4 dB
range in each direction, and a programmable filter
is included to enable Hybrid Balancing to be ad-
justed to suit a wide range of loop impedance con-
ditions.
Both transformer and active SLIC interface circuits
with real or complex termination impedances can
be balanced by this filter, with cancellation in ex-
cess of 30 dB being readily achievable when meas-
ured across the passbandagainst standardtest ter-
mination networks.
To enable COMBO IIG to interface to the SLIC con-
trol leads, a number of programmable latches are
included ; each may be configured as either an in-
put or an output. The TS5070 provides 6 latches
and the TS5071 5 latches.
1/32
TS5070 - TS5071
TS5070 PIN FUNCTIONALITY (PLCC28)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
GND
VF
R
0
V
SS
NC
NC
IL3
IL2
FS
R
D
R
1
D
R
0
CO
CI
CCLK
CS
MR
BCLK
MCLK
D
X
0
D
X
1
TS
X
0
TS
X
1
FS
X
IL5
IL4
IL1
IL0
V
CC
VF
X
I
Function
Ground Input (+0V)
Analog Output
Supply Input (-5V)
Not Connected
Not Connected
Digital Input or Output defined by LDR register content
Digital Input or Output defined by LDR register content
Digital input
Digital input sampled by BCLK falling edge
Digital input sampled by BCLK falling edge
Digital output (shifted out on CCLK rising edge)
Digital input (sampled on CCLK falling edge)
Digital input (clock)
Digital input (chip select for CI/CO)
Digital Input
Digital input (clock)
Digital input
Digital output clocked by BCLK rising edge
Digital output clocked by BCLK rising edge
Open drain output (pulled low by active DX0 time slot)
Open drain output (pulled low by active DX1 time slot)
Digital input
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Supply input (+5V)
Analog input
TS5070 FUNCTIONAL DIAGRAM
VCC=+5V
VFXI
ENCODER
AZ
VSS=-5V
TX GAIN
TX TIME SLOT
TX
REGISTER
DX0
DX1
TSX0
HYBRID
BALANCE
FILTER
HYBAL 1
HYBAL 2
HYBAL 3
Vref
TIME-SLOT
ASSIGNMENT
CTL REG.
TSX1
FSX
BCLK
FSR
VFRO
RX
REGISTER
DR0
DR1
MCLK
GND
TS5070/71
RX TIME SLOT
DECODER
IL5
IL4
IL3
IL2
IL1
IL0
D94TL135
MR
RX GAIN
CS
CONTROL
INTERFACE
CCLK
CO
CI
INTERFACE
LATCHES
LATCH DIR
LATCH CONT.
2/32
TS5070 - TS5071
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
SS
V
IN
I
O
T
stg
T
lead
V
CC
to GND
V
SS
to GND
Voltage at VFXI
Voltage at Any Digital Input
Current at VFRO
Current at Any Digital Output
Storage Temperature Range
Lead Temperature Range (soldering, 10 seconds)
Parameter
Value
7
–7
V
CC
+ 0.5 to V
SS
– 0.5
V
CC
+ 0.5 to GND – 0.5
±
100
±
50
– 65, + 150
300
Unit
V
V
V
V
mA
mA
°C
°C
3/32
TS5070 - TS5071
PIN CONNECTIONS
PLCC28
TS5070FN
DIP20
TS5071N
POWER SUPPLY, CLOCK
Name
V
CC
V
SS
GND
BCLK
Pin
Type
S
S
S
I
TS5070
FN
27
3
1
16
TS5071
N
19
3
1
12
Function
Positive Power
Supply
Negative
Power Supply
Ground
Bit Clock
+5V
±
5%
– 5 V
±
5%
All analog and digital signals are referenced to this pin.
Bit clock input used to shift PCM data into and out of the
D
R
and D
X
pins. BCLK may vary from 64 kHz to 4.096
MHz in 8 kHz increments, and must be synchronous with
MCLK (TS5071 only).
Master clock input used by the switched capacitor filters
and the encoder and decoder sequencing logic. Must be
512 kHz, 1. 536/1. 544 MHz,
2.048 MHz or 4.096 MHz and synchronous with BCLK.
BCLK and MCLK are wired together in the TS5071.
Description
MCLK
I
17
12
Master Clock
4/32
TS5070 - TS5071
TRANSMIT SECTION
Name
FS
X
Pin
Type
I
TS5070
FN
22
TS5071
N
15
Function
Transmit
Frame Sync.
Description
Normally a pulse or squarewave waveform with an 8 kHz
repetition rate is applied to this input to define the start of
the transmit time-slot assigned to this device (non-delayed
data mode) or the start of the transmit frame (delayed
data mode using the internal time-slot assignment
counter).
This is a high–impedance input. Voice frequency signals
present on this input are encoded as an A–law or
µ–law
PCM bit stream and shifted out on the selected D
X
pin.
D
X
1 is available on the TS5070 only, D
X
0 is available on
all devices. These transmit data TRI–STATE
®
outputs
remain in the high impedance state except during the
assigned transmit time–slot on the assigned port, during
which the transmit PCM data byte is shifted out on the
rising edges of BCLK.
TS
X
1 is available on the TS5070 only.
TS
X
0 is available on all devices. Normally these opendrain
outputs are floating in a high impedance state except
when a time–slot is active on one of the D
X
outputs, when
the apppropriate TS
X
output pulls low to
enable a backplane line–driver. Should be strapped to
ground (GND) when not used.
VF
X
I
I
28
20
Transmit
Analog
D
X
0
D
X
1
0
0
18
19
13
–
Transmit Data
TS
X
0
TS
X
1
0
0
20
21
14
–
Transmit
Time–slot
RECEIVE SECTION
Name
FS
R
Pin
Type
I
TS5070
FN
8
TS5071
N
6
Function
Receive Frame
Sync.
Description
Normally a pulse or squarewave waveform with an 8 kHz
repetition rate is applied to this input to define the start of
the receive time–slot assigned to this device (non-delayed
frame mode) or the start of the receive frame (delayed
frame mode using the internal time-slot assignment
counter.
The receive analog power amplifier output, capable of
driving load impedances as low as 300
Ω
(depending on
the peak overload level required). PCM data received on
the assigned D
R
pin is decoded and appears at this output
as voice frequency signals.
D
R
1 is available on the TS5070 only, D
R
0 is available on
all devices. These receive data input(s) are inactive
except during the assigned receive time–slot of the
assigned port when the receive PCM data is shifted in on
the falling edges of BCLK.
VF
R
0
0
2
2
Receive Analog
D
R
0
D
R
1
I
I
10
9
7
–
Receive Data
5/32
PCB设计
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