SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Product List
SM5964AL25, 25MHz 64KB internal flash MCU
SM5964AC40, 40MHz 64KB internal flash MCU
Feature
Working Voltage: 3.0V ~ 3.6V For L Version.
4.5V ~ 5.5V For C Version.
80C51 Central Processor Unit (CPU)
64K x 8 on chip flash memory with In-
System-Programming(ISP) capability
1024 x 8 RAM, expandable externally to
64KB
Two standard 16-bit timers/counters
An additional 16-bit timer/counter coupled to
a capture and compare register.
Two 8-bit / 5-bit resolution
Pulse-Width-Modulation (PWM) outputs
Four 8-bit I/O ports.(For PDIP package)
Four 8-bit I/O ports plus one 4-bit I/O port.
(For PLCC or QFP package)
TWSI-bus serial I/O port with master and
slave functions
Full-duplex UART
7 interrupt sources with 2 priority levels
Temperature range (0℃ to +70℃)
Software enable/disable ALE output pulse
Wake-up from POWER-DOWN mode by
external interrupt or H/W RESET.
ISP service program space configurable in
N*512 byte (N=0 to 8) size
General Description
The SM5964A is an 8-bit single-chip micro-
controller manufactured in an advanced CMOS
process with on chip flash memory. It supports In-
System Programming (ISP) function and is a
derivative of the 8052 micro-controller family. The
SM5964A has the same instructions set as the 80C51.
The SM5964A contains a 64KB on chip program
flash, a volatile 1024 x 8 data RAM, four 8-bit I/O
ports, one 4-bit I/O port, two 16-bit timer/event
counters, and an additional 16-bit timer coupled to
capture and compare latches, a two-priority-level,
nested interrupt structure, two pulse-width-
modulation (PWM) outputs, two serial interfaces
(UART and TWSI bus). For system that requires
extra capability the SM5964A can be expanded using
standard LVTTL compatible memory and logic.
In addition, The SM5964A has two software
selectable modes of power saving – IDLE mode and
POWER-DOWN mode. The IDLE mode freezes the
CPU while allowing the RAM, timer, serial ports, and
interrupt system to continue functioning. The
POWER-DOWN mode saves the RAM contents but
freezes the oscillator, causing all other chip functions
to be inoperative.
The on chip flash memory can store data while the
program is running. It also can upgrade the user
program by down-load new code form PC or other
devices. The chip is considered as a small integrated
system.
Ordering Information
SM5964AihhkL
yymmv
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
yy: year
mm: month
v: version identifier { , A, B, ...}
L: PB free identifier {no text is Non-PB free, “P” is PB free}
Taiwan
6F, No.10-2 Li- Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
TEL: 886-3-567-1820
886-3-567-1880
FAX: 886-3-567-1891
886-3-567-1894
Specifications subject to change without notice contact your sales representatives for the most recent information.
1
Ver 2.5 SM5964A 02/2008
SyncMOS Technologies International, Inc.
Package Spec.
K
Package
Pin / PAD
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Pin Configuration
J
Q
P
AD4/P0.4
44L PLCC
44L PQFP
40L PDIP
AD7/P0.7
AD6/P0.6
AD5/P0.5
#EA
P4.1
Figure 1
Figure 2
Figure 3
A14/P2.6
#PSEN
A16/P2.7
A13/P2.5
23
22
12
ALE
6
P1.5
SCL/P1.6
SDA/P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
17
18
7
1
40
39
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
#EA
P4.1
ALE
#PSEN
A16/P2.7
A14/P2.6
29
28
A13/P2.5
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VDD
P4.2
T2/P1.0
T2EX/P1.1
PWM0/P1.2
PWM1/P1.3
P1.4
34
33
A12/P2.4
A11/P2.3
A10/P2.2
A9/P2.1
A8/P2.0
P4.0
VSS
XTAL1
XTAL2
#RD/P3.7
44
#WE/P3.6
SCL/P1.6
P1.5
RXD/P3.0
TXD/P3.1
T0/P3.4
Figure 1
44L PLCC Package
Figure 2 44L PQFP Package
Figure 3
44
40L PDIP Package
Specifications subject to change without notice contact your sales representatives for the most recent information.
2
Ver 2.5 SM5964A 02/2008
#INT1/P3.3
SDA/P1.7
#INT0/P3.2
T1/P3.5
RES
P4.3
11
1
SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Block Diagram
PWM0
PWM1
T2
T2EX
RxD
(3)
TxD
(3)
(1)
(1)
(1)
(1)
Xtal1
Xtal2
EA
CPU
ALE
PSEN
RD
WR
(3)
(3)
UART
Int-RAM
256x8
IAP
FLASH
64Kx8
Ext-RAM
768x8
PWM
Timer2
C51
CORE
iBUS
Timer0
Timer1
INT
PDWU
Port0
Parallel I/O ports & Ext. Bus
Port1
Port2
Port3
Port4
TWSI
(1)
(1)
(3)
(3)
(3)
(3)
(3)
(3)
Notes:
(1): Alternate function of P1
(3): Alternate function of P3
Specifications subject to change without notice contact your sales representatives for the most recent information.
RES
T0
T1
INT0
INT0
INT1
INT1
3
P0
P4
P1
P2
SCL
SDA
Ver 2.5 SM5964A 02/2008
P3
SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Pin Description
MNEMONIC
VDD
P0.0 – P0.7
PDIP 40 pin
40
39,38,37,36
35,34,33,32
PQFP 44 Pin
38
37,36,35,34
33,32,31,30
PLCC 44 pin
44
43,42,41,40
39,38,37,36
Names and Functions
Power supply:
power supply pin during normal operations and power saving modes.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have
1s written to them become floating and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
An 8-bits bidirectional I/O port with internal pull-ups on all pins.
Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL).
Alternate function of SM5964A include：
Port Pin
Alternative function
P1.0
T2： TIMER2 clock output
P1.1
T2EX：TIMER2 reload/capture DIR.
P1.2
PWM0：PWM channel 0 output
P1.3
PWM1：PWM channel 1 output
P1.6
SCL：TWSI bus clock
P1.7
SDA：TWSI bus data
Reset:
A high on this pin for two machine cycles while the oscillator is
running resets the device. An internal resistor to VSS permits a
power-on reset using only an external capacitor to VCC.
Port 2:
Port 2 is an 8-bits bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 2 pins that are
externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2
emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that
uses 16-bits addresses (MOVX @DPTR). In this application, it uses
strong internal pull-ups when emitting 1s. During accesses to
external data memory that uses 8-bits addresses (MOV @Ri), port 2
emits the contents of the P2 special function register.
Port 3:
Port 3 is an 8-bits bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves
the special features.
Port Pin
Alternative function
P3.0
RxD UART input
P3.1
TxD UART output
P3.2
#EX0 external interrupt 0
P3.3
#EX1 external interrupt 1
P3.4
T0: Timer 0 external input
P3.5
T1: Timer 1 external input
P3.6
#WR External data memory write strobe
P3.7
#RD External data memory read strobe
P1.0 – P1.7
1,2,3,4,
5,6,7,8
40,41,42,43,
44,1,2,3
2,3,4,5,
6,7,8,9
RST
9
4
10
P2.0 – P2.7
21,22,23,24,
25,26,27,28
18,19,20,21
22,23,24,25
24,25,26,27,
28,29,30,31
P3.0 – P3.7
10,11,12,13
14,15,16,17
5,7,8,9,
10,11,12,13
11, 13,14,15,
16,17,18,19
Specifications subject to change without notice contact your sales representatives for the most recent information.
4
Ver 2.5 SM5964A 02/2008
SyncMOS Technologies International, Inc.
SM5964A
MNEMONIC
ALE
PDIP 40 pin
30
PQFP 44 Pin
27
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
PLCC 44 pin
Names and Functions
33
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted
twice every machine cycle, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to
external data memory. Setting SFR SCONF.0 can disable ALE. With
this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable:
The read strobe to external program memory. When executing code
from the external program memory, #PSEN is activated twice each
machine cycle, except that two #PSEN activations are skipped
during each access to external data memory. #PSEN is not activated
during fetches from internal program memory.
External Access Enable:
#EA must be externally held low to enable the device to fetch code
from external program memory locations. If #EA is held high, the
device executes from internal program memory.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
#PSEN
29
26
32
#EA
31
29
35
X1
19
15
21
X2
18
14
20
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
Ver 2.5 SM5964A 02/2008
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