FemtoClock NG
®
Clock Synthesizer
ICS843N571I
DATA SHEET
General Description
The ICS843N571I is a PLL based clock synthesizer for use in
Ethernet applications. The device uses IDT’s fourth generation
FemtoCLock
®
NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. Using IDT’s
latest FemtoClock NG PLL technology, the ICS843N571I achieves
<0.3ps RMS phase jitter performance.
ICS843N571I can synthesize 100MHz, 125MHz, 156.25MHz and a
low frequency 33.33MHz CPU clock from a single device. Six
LVCMOS outputs also serve as additional buffering of the 25MHz
crystal reference.
Features
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Fourth generation FemtoClock
®
Next Generation (NG) technology
Seven single-ended LVCMOS outputs, 30
Ω
output impedance
Three LVPECL output pairs
One differential LVPECL (QA, nQA) output pair: 156.25MHz
Two selectable differential LVPECL output pairs (QB, nQB and
QC, nQC): 100MHz and 125MHz
One single-ended LVCMOS (QD0) 33.33MHz CPU clock
Selectable external crystal or single-ended input source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
FemtoClock NG VCO frequency: 2.5GHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.283ps (typical)
Power supply noise rejection PSNR: -80dB
3.3V supply voltage
-40C to 85C ambient operating temperature
Available in lead-free (RoHS 6) packages
Pin Assignment
FORCE_LOW
nc
QREF5
40 39 38 37 36 35 34 33 32 31
V
EE
V
CC
QREF0
QREF1
V
CC
XTAL_IN
XTAL_OUT
REFCLK
REFSEL
V
EE
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
V
CC
nQA
QB
nQB
V
CC
V
CC
QA
nc
nc
nc
30
29
QREF3
QREF2
V
CC
FREQSEL
V
CC
V
CC
V
CC
QD0
nQC
QC
ICS843N571I
40-Lead VFQFN
6mm x 6mm x 0.925mm
package body
K Package
Top View
QREF4
28
27
26
25
24
23
22
21
V
CC
V
CC
V
CC
ICS843N571AKI REVISION A SEPTEMBER 29, 2011
1
©2011 Integrated Device Technology, Inc.
V
EE
V
CC
nc
ICS843N571I Data Sheet
FEMTOCLOCK NG
®
CLOCK SYNTHESIZER
Block Diagram
REFSEL
Pullup
QREF 0
XTAL_IN
25MHz
XTAL_OUT
OSC
QREF 1
1
0
QREF 2
QREF 3
QREF 4
QREF 5
REFCLK
Pulldown
25MHz
PF
+
CP
FemtoClock NG
VCO
÷16
QA
nQA
÷100
÷25
0
1
QB
nQB
FREQSEL
Pullup/Pulldown
3 -State
Decoder
0
QC
nQC
÷20
1
÷75
FORCE_LOW
Pulldown
QD0
ICS843N571AKI REVISION A SEPTEMBER 29, 2011
2
©2011 Integrated Device Technology, Inc.
ICS843N571I Data Sheet
FEMTOCLOCK NG
®
CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 10, 34
Name
V
EE
Power
Type
Description
Negative supply pins.
Power supply pins.
Pins 2, 28, 33 – power supply connection for the 25MHz LVCMOS outputs
Pin 5 – power supply connection for the crystal oscillator
Pins 11, 15, 26, 35 – power supply connection for the dividers and other core
circuitry
Pin 16 (vposO) – power supply connection for the differential LVPECL outputs
Pin 24, 25 – power supply connection for the 33MHz LVCMOS output
Pin 39 – power supply connection for the digital logic
Pin 40 – power supply connection for the PLL
Single-ended outputs. 3.3V LVCMOS/LVTTL reference levels.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown
Pullup
Single-ended LVCMOS/LVTTL reference clock input.
Reference select pin. When HIGH, selects crystal. When LOW, selects
REFCLK. See Table 3A. LVCMOS/LVTTL interface levels.
No connect.
Output
Output
Output
Output
Input
Input
Pullup/
Pulldown
Pulldown
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Single-ended output. 3.3V LVCMOS/LVTTL reference levels.
Frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Forces the QD0 output into a low state. See Table 3C.
LVCMOS/LVTTL interface levels.
2, 5, 11, 15,
16, 24, 25,
26, 28, 33,
35, 39, 40
V
CC
Power
3, 4,
29, 30,
31, 32
6,
7
8
9
12, 13, 14,
36, 38
17, 18
19, 20
21, 22
23
27
37
QREF0, QREF1,
QREF2, QREF3,
QREF4, QREF5
XTAL_IN,
XTAL_OUT
REFCLK
REFSEL
nc
QA, nQA
QB, nQB
QC, nQC
QD0
FREQSEL
FORCE_LOW
Output
Input
Input
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QD0,
QREF[0:5]
QD0,
QREF[0:5]
V
CC
= 3.6V
Test Conditions
Minimum
Typical
2
6
51
51
30
Maximum
Units
pF
pF
k
Ω
k
Ω
Ω
ICS843N571AKI REVISION A SEPTEMBER 29, 2011
3
©2011 Integrated Device Technology, Inc.
ICS843N571I Data Sheet
FEMTOCLOCK NG
®
CLOCK SYNTHESIZER
Function Tables
Table 3A. REFSEL Function Table
Inputs
REFSEL
0
1 (default)
REFCLK
XTAL_IN, XTAL_OUT
Input Source
Table 3B. FREQSEL Function Table
Inputs
FREQSEL
0
1
Float (default)
Output Frequency (MHz)
QB, nQB
125
100
125
QC, nQC
125
100
100
Table 3C. FORCE_LOW Function Table
Inputs
FORCE_LOW
0 (default)
1
Output Frequency (MHz)
QD0
33.33
Disabled
ICS843N571AKI REVISION A SEPTEMBER 29, 2011
4
©2011 Integrated Device Technology, Inc.
ICS843N571I Data Sheet
FEMTOCLOCK NG
®
CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.63V
0V to V
CC
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 0.3V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
No Load
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
250
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High
Voltage
Input Low
Voltage
Input Medium
Voltage
Input
High Current
Input
Low Current
REFSEL, FORCE_LOW
FREQSEL
REFSEL, FORCE_LOW
FREQSEL
FREQSEL
REFCLK,
FREQSEL, FORCE_LOW
REFSEL
REFCLK, FORCE_LOW
REFSEL, FREQSEL
I
IL
V
OH
V
OL
V
CC
= V
IN
= 3.6V
V
CC
= V
IN
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.3V ± 0.3V
V
CC
= 3.3V ± 0.3V
-5
-150
2.3
0.8
V
CC
/2 - 0.1
Test Conditions
Minimum
2
V
CC
- 0.4
-0.3
0.8
0.4
V
CC
/2 + 0.1
150
5
V
V
V
µA
µA
µA
µA
V
V
Typical
Maximum
V
CC
+ 0.3
Units
V
V
IL
V
IM
I
IH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
CC
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
ICS843N571AKI REVISION A SEPTEMBER 29, 2011
5
©2011 Integrated Device Technology, Inc.
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