ICS84329-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS84329-01 is a general purpose, single output high
frequency synthesizer. The VCO operates at a frequency range
of 200MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of thecrystal frequency divided by
16. The VCO and output frequency can be programmed
using the serial or parallel interfaces to the configuration logic.
The output can be configured to divide the VCO frequency by
1, 2, 4, and 8. Output frequency steps as small as 125kHz to
1MHz can be achieved using a 16MHz crystal depending on
the output dividers.
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface
Output frequency range: 25MHz to 700MHz
VCO range: 200MHz to 700MHz
Parallel interface for programming counter
and output dividers during power-up
Serial 3 wire interface
RMS Period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
V
EE
TEST
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL2
XTAL1
nc
nc
V
CCA
S_LOAD
S_DATA
S_CLOCK
V
CC
FOUT
nFOUT
V
EE
XTAL1
OSC
XTAL2
÷
16
PLL
PHASE DETECTOR
1
VCO
÷
M
0
÷
1
÷
2
÷
4
÷
8
FOUT
nFOUT
ICS84329-01
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
nFOUT
FOUT
TEST
V
CC
V
CC
V
EE
V
EE
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL1
26
27
28
1
18
17
N1
N0
M8
M7
M6
M5
M4
ICS84329-01
16
28-Lead PLCC
15
11.6mm x 11.4mm x 4.1mm
2
14
V Package
3
13
Top View
4
5
XTAL2
12
6
Vcc
7
nP_LOAD
8
M0
9 10 11
M1
M2
M3
84329AM-01
www.idt.com
1
REV. D AUGUST 7, 2010
ICS84329-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS84329-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A series-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the oscil-
lator is divided by 16 prior to the phase detector. With a
16MHz crystal this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 200MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by
adjusting the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being
sent to each of the LVPECL output buffers. The divider pro-
vides a 50% output duty cycle.
The programmable features of the ICS84329-01 support
two input modes to program the M divider and N output
divider. The two input operational modes are parallel and
serial.
Figure 1
shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is LOW. The data on in-
puts M0 through M8 and N0 through N1 is passed directly
T2
0
0
0
0
1
1
1
1
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
t
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is
Mode 000 (shift register out) when operating in the parallel
input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as fol-
lows:
fxtal x
fVCO =
M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Func-
tion Table. Valid M values for which the PLL will achieve
lock are defined as 200
≤
M
≤
511. The frequency out is
defined as follows:
fout = fVCO = fxtal x M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The con-
tents of the shift register are loaded into the M divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and
N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider on each
rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T2:T0. The internal
registers T2:T0 determine the state of the TEST output as
follows:
TEST Output
fOUT
Shift Register Out
fOUT
High
fOUT
PLL Reference Xtal ÷ 16
fOUT
M (non 50% Duty M divider)
fOUT
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
VCO ÷
fOUT
LVCMOS Output Frequency < 200MHz
Low
S_CLOCK ÷ M
(non 50% Duty Cycle M divider)
fOUT ÷ 4
S
ERIAL
L
OADING
T2
S
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
84329AM-01
www.idt.com
2
REV. D AUGUST 7, 2010
ICS84329-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Name
M0, M1, M2, M3,
M4, M5, M6, M7, M8
N0, N1
V
EE
TEST
V
CC
nFOUT, FOUT
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
XTAL1, XTAL2
Type
Input
Input
Power
Output
Power
Output
Input
Input
Input
Power
Unused
Input
Pullup
Pullup
Description
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Clocks the serial data present at S_DATA input into the shift register
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
Pulldown
LVCMOS / LVTTL interface levels.
Analog supply pin.
No connect.
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into
the M divider, and when data present at N1:N0 sets the N output divider value.
nP_LOAD
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84329AM-01
www.idt.com
3
REV. D AUGUST 7, 2010
ICS84329-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
nP_LOAD
X
L
↑
H
H
H
M
X
Data
Data
X
X
X
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
S_LOAD
X
X
L
L
↑
↓
S_CLOCK
X
X
X
↑
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
N
X
Data
Data
X
X
X
H
X
X
L
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
200
201
202
203
•
•
509
510
511
M Divider
200
201
202
203
•
•
509
510
511
256
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
0
0
0
0
•
•
1
1
1
16
M4
0
0
0
0
•
•
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
4
M2
0
0
0
0
•
•
1
1
1
2
M1
0
0
1
1
•
•
0
1
1
1
M0
0
1
0
1
•
•
1
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
200
100
50
25
Maximum
700
350
175
87.5
84329AM-01
www.idt.com
4
REV. D AUGUST 7, 2010
ICS84329-01
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CC
+ 0.5V
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. DC P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
110
15
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
Parameter
Input High Voltage
S_LOAD, nP_LOAD,
S_DATA, S_CLOCK,
M0:M8, N0:N1
S_LOAD, nP_LOAD,
Input Low Voltage
S_DATA, S_CLOCK,
M0:M8, N0:N1
M0-M8, N0, N1,
nP_LOAD
Input High Current
S_LOAD,
S_DATA, S_CLOCK
M0-M8, N0, N1,
nP_LOAD
Input Low Current
S_LOAD,
S_DATA, S_CLOCK
Output High Voltage; NOTE 1
Test Conditions
Minimum Typical
2
Maximum
V
CC
+ 0.3
Units
V
V
IL
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.8
5
150
V
µA
µA
µA
µA
V
I
IH
I
IL
V
OH
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
CC
/2. See figure "3.3V Output Load Test Circuit" in the
"Parameter Measurement Information" section.
0.5
V
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
84329AM-01
www.idt.com
5
REV. D AUGUST 7, 2010
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